DSP101 Burr-Brown Corporation, DSP101 Datasheet
DSP101
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DSP101 Summary of contents
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... Both the DSP101 and DSP102 are packaged in stan- dard, low-cost 28-pin plastic DIP packages. Each is offered in two performance grades to match applica- tion requirements ...
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... +2 Serial; MSB first; 16/18-bit and Cascaded 32-bit Mode = 4mA 0 = 4mA +2.4 Can only be used to drive crystal oscillator. 2mA +4.75 +5 –5.25 –5 +4.75 +5 250 30 – –65 2 DSP101KP DSP102KP MAX MIN TYP MAX –86 –91 – ...
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... XCLK = 40f = 8MHz; Using 100 Frequency (kHz 100 Frequency (kHz) – 1kHz, ±2.75V IN –85 SINAD –90 THD SNR –95 SFDR –100 125 Ambient Temperature (°C) DSP101/102 ® ...
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... Input (0dB ±0.275V Input (–20dB ±2.75mV Input (–60dB 0.1 1 Input Frequency (kHz) ® DSP101/102 (CONT) = 200kHz; External Clock Input at OSC1 = 80f S DYNAMIC PERFORMANCE vs TEMPERATURE – 1kHz, ±2.75V –75 80 –80 85 –85 90 –90 95 –95 100 – ...
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... Digital Ground. +5V Digital Power. D Conversion Clock In. Conversion Clock Out. Can drive multiple DSP101/DSP102s to synchronize conversion. Select Synch Format In. If HIGH, SYNC will be active High. If LOW, SYNC will be active Low. See timing diagram (Figure 1). Oscillator Point 1 Input/External Clock In. If using external clock, drive with 74HC logic levels. ...
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... Digital Ground. Digital Ground. +5V Digital Power. D Conversion Clock In. Conversion Clock Out. Can drive multiple DSP101/ DSP102s to synchronize conversion. Select Synch Format In. If HIGH, SYNC will be active High. If LOW, SYNC will be active Low. See timing diagram (Figure 1). Oscillator Point 1 Input / External Clock In. If using external clock, drive with 74HC logic levels ...
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... FIGURE 1. DSP101 and DSP102 Timing. DSP101/102 7 ® ...
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... BASIC OPERATION Figure 2 shows the minimum connections required to oper- ate the DSP101. The falling edge of a convert command on pin 21 puts the internal sampling capacitor array into the hold state. The falling edge on pin 21 also starts the process ...
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... XCLK, the system bit clock. Following a convert command falling edge, pin 21 must be held LOW at least 50ns. Convert commands can be sent to the DSP101 and DSP102 completely asynchronous to other clocks in the system. This allows external events to be used to trigger conversions. ...
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... XCLK. Figure 4 shows the operation of the internal data shift registers on the DSP102. The DSP101 is basically similar, but includes only the top of the figure, showing the SOUTA path. 10 18-bit Shift Register ...
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... Digital 10µF NOTES: (1) Pin 1 and pin 26 must be bypassed with 10µF tantalum capacitors, on both the DSP101 and DSP102. (2) Protection from power supply momentary overrange. FIGURE 6. DSP101 or DSP102 Power Supply Connections. long enough for internal analog circuitry to settle suffi- ciently between bit decisions to insure rated accuracy. Bit decisions in the A/D are then made on the rising edge of CLKIN ...
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... XCLK. Between convert commands, the information input on TAG (on the DSP101 TAGA and TAGB (on the DSP102) will be clocked into the output shift register on the rising edges of XCLK. Since this is an 18-bit shift register, ...
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... FIGURE 8. DSP101 or DSP102 Optional MSB and Offset Adjust. NOISE AND BIPOLAR ZERO ERROR The equivalent input noise and bipolar zero error of the DSP101 and DSP102 is shown in the typical performance section for both channels on a DSP102. The inputs to both channels were grounded, and the results of 5,000 conver- sions was recorded ...
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... Pin 28 (AGND) on both the DSP101 and the DSP102 is the most critical, and care should be taken to make this pin as close as possible to the same potential as the system analog ground. ...
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... Where required by specific applications, offsets can be ad- justed using the circuit of Figure 8. When not adjusted, VOS (pin 4) on the DSP101, and VOSA (pin 4) and VOSB (pin 23) on the DSP102, should be left open. If these pins are con- nected to traces on the board, they should be bypassed to ground with 0 ...
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... Q2. In many systems, galvanic isolation of signals is required. Using opto-couplers on the serial data lines in Figure 9 allows a fully isolated system to be built using a DSP101 and only three couplers across the barrier (for serial data, XCLK and SYNC.) MULTIPLEXING INPUTS TO THE DSP101 ...
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... Sync output of the DSP101. The channel address tag data is then clocked into the DSP101 Tag input (pin 18) by the bit clock, while the conversion data is clocked out the other end of the ±2.75V Analog Input ...
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... See Burr-Brown DSP201/202 product data sheet for full description of this DAC. FIGURE 15. Two-Channel Analog Input and Output System with TMS320C30 in Cascade Mode. ® DSP101/102 In all cases, the DSP101 and DSP102 will transmit data MSB-first, and the TMS320Cxx needs to be programmed for this. Figure 11 shows a circuit for using the TMS320C25 or ...
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... Convert Command, minimizing additional circuitry and syn- chronizing the timing signals to the processor’s master 2 ±2.75V Analog Input FIGURE 16. Using DSP101 with TMS320C25. DSP102 ±2.75V Analog Input XCLK VINA ...
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... High synchronization pulse on SYNC (pin 15) after a con- vert command is received by the A/D. Timing is shown in Figure 1. USING DSP101 AND DSP102 WITH AT&T DSP ICS Figures 11, 19, 20, and 21 show how to use the DSP101 and 2 VIN ±2.75V Analog Input NOTES: (1) DSP56001 programmed for MSB bit first data. (2) DSP56001 data may be either 16-bit or 24-bit. ...
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... Channel B NOTES: (1) DSP32C programmed 32-bit data MSB bit first. (2) Data format is Channel A, 16 bits, MSB first, then Channel B. FIGURE 21. Using DSP102 with DSP32C in Cascade Mode. The same basic circuit can be used to connect a DSP101 to the ADSP2101. Figure 11 indicates how to build a complete analog I/O system using either the ADSP2101 or the ADSP2105 with a DSP101 and a Burr-Brown DSP201 D/A ...
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... FIGURE 23. Using DSP101 with ADSP-2105. DEM-DSP102/202 EVALUATION BOARD An evaluation fixture, the DEM-DSP102/202, is available to simplify evaluation of the DSP101 and DSP102, and the companion digital-to-analog converters, the single DSP201 and dual DSP202. The DEM-DSP102/202 comes complete with a socketed DSP102 and DSP202, a breadboard area, TTL I/O headers and differential line drivers for data trans- ® ...