DSP101 Burr-Brown Corporation, DSP101 Datasheet - Page 19

• Manufacturer Part Number: DSP101
• Description: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: Burr-Brown Corporation

USING TMS320C31 TO GENERATE
ALL CONTROL SIGNALS
Figure 17 shows a circuit for using the TMS320C31 with a
DSP102 and a Burr-Brown DSP202 D/A to provide a two
channel analog I/O system. The flexibility of the TMS320C31
allows it to generate the data transfer clock (XCLK) and the
Convert Command, minimizing additional circuitry and syn-
chronizing the timing signals to the processor’s master
FIGURE 16. Using DSP101 with TMS320C25.
FIGURE 17. Two Channel Analog I/O Using TMS320C31.
TABLE II. TMS320C31 Register Settings for 44.1kHz Con-
±2.75V Analog Input
NOTE: Assumes TMS320C31 has 32MHz Master Clock.
±2.75V Analog Input
SERIAL PORT
Port Global Control Register
FSX/DX/CLKX Port Control Register
FSR/DR/CLKR Port Control Register
Receive/Transmit Timer Control Register
TIMER
Timer Global Control Register
Timer Period Register
Channel A
Channel B
10pF
version Rate in Figure 17.
1M
±2.75V Analog Input
10pF
12.288MHz
VINA
VINB
OSC2
OSC1
DSP102
SOUTA
SOUTB
SYNC
CASC
XCLK
CONV
2
SSF
VIN
0x0EBC040
0x00000111
0x00000111
0x0000000F
0x000002C1
0x000000B5
DSP101
NOTES: (1) TMS320C25 FSR external, 16-bit data.
+5V
CONV
NC
+5V
SYNC
SOUT
XCLK
SSF
CLKR0
DR0
FSR0
16
15
20
12
21
TMS3200C31
TCLK0
+5V
19
TTL Bit
Clock
clock. In this circuit, the DSP102 and DSP202 are used in
their Cascade modes, transmitting and receiving two chan-
nels of data in a single 32-bit word. (See the Cascade Mode
section above.)
Table II shows how to set up the circuit in Figure 17 for a
44.1kHz conversion rate for both channels of the DSP102
A/D and both channels of the DSP202 D/A. Both inputs and
outputs will be simultaneously converted.
CLKX0
FSX0
DX0
+5V
+5V
+5V
XCLK
FSX
TXD
Conversion Rate
TMS320C25
Generator
XCLK
SINA
SINB
SYNC
SSF
SWL
CASC
CONV
DSP202
DSP101/102
VOUTA
VOUTB
±3V Analog Output
±3V Analog Output
Channel A
Channel B
®