IDT72V231L10J8 IDT, Integrated Device Technology Inc, IDT72V231L10J8 Datasheet - Page 9

• Manufacturer Part Number: IDT72V231L10J8
• Description: IC FIFO SYNC 2048X9 10NS 32-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V231L10J8

• Function: Synchronous
• Memory Size: 18.4K (2K x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V231L10J8

NOTE:
1. t
NOTE:
1. When t
Q
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
(If Applicable)
WCLK
WEN2
REN2
WEN1
RCLK
REN1,
0
the rising edge of RCLK and the rising edge of WCLK is less than t
When
The Latency Timings apply only at the Empty Boundary (EF = LOW).
- Q
SKEW1
OE
EF
8
Q
D
t
WCLK
WEN2
0
SKEW1
SKEW1
WEN1
REN2
is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
RCLK
0
REN1,
- Q
- D
OE
EF
≥ minimum specification, t
< minimum specification, t
8
8
t
ENS
t
OLZ
t
FRL
ENS
t
t
FRL
ENS
ENH
= 2t
= t
CLK
CLK
t
t
DS
t
SKEW1
CLKH
+ t
+ t
t
REF
t
SKEW1
SKEW1
A
t
OE
or t
Figure 7. First Data Word Latency Timing
CLK
t
NO OPERATION
CLK
+ t
Figure 6. Read Cycle Timing
SKEW1
D
SKEW1
0
(First Valid Write)
, then EF may not change state until the next RCLK edge.
t
t
CLKL
OLZ
t
t
REF
FRL
VALID DATA
(1)
9
t
OHZ
t
ENS
D
1
t
OE
t
SKEW1
(1)
t
A
t
REF
D
2
COMMERCIAL AND INDUSTRIAL
D
0
t
A
TEMPERATURE RANGES
OCTOBER 22, 2008
D
3
D
4092 drw09
4092 drw08
1