UPD98405 NEC, UPD98405 Datasheet - Page 11

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1)
PHR/W_B
(shared with
PHYALM)
PHOE_B
PHCE_B
(shared with
SD)
PHINT_B
(shared with
REFCLK)
PHRST_B
Pin Name
Caution The PHCE_B/SD pins are multiplexed pins and their functions differ depending on whether the
internal PHY mode or external PHY mode is selected (by using the PHM bit of the GMR register).
Because the PHCE_B/SD pins change the mode between input and output depending on the
selected mode, be sure to correctly set the PHM bit of the GMR register.
Pin No.
266
265
267
268
264
I/O
O
O
O
O
I
I/O Level
Data Sheet S12689EJ2V0DS00
TTL
TTL
TTL
TTL
TTL
PHY read/write.
The PD98405 indicates the PHY layer device control direction
by using this pin.
PHY layer output enable.
The PD98405 enables output by the PHY layer device by
making this signal low.
PHY layer chip enable.
The PD98405 makes this signal low when it accesses the PHY
layer device.
PHY layer interrupt.
This pin inputs an interrupt signal to the PD98405 from the
PHY layer device. The PHY layer device informs the PD98405
that it has an interrupt source by inputting a low level to this pin.
Pull up this pin when it is not used.
This signal is used to reset the PHY layer device. The
when a low level is input to the RST_B pin or when software
reset is executed.
PHY layer reset.
PD98405 keeps this pin low for the duration of 17 clock cycles
1: Read
0: Write
Function
PD98405
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