AN1356 STMicroelectronics, AN1356 Datasheet
AN1356
Related parts for AN1356
AN1356 Summary of contents
Page 1
... MCU is off line and not involved while memory is being programmed. IAP of memory means that the MCU participates in programming memory, which is important for systems that must be online while updating firmware. Often, ISP is well suited for manufacturing, while IAP is appropriate for field updates. PSD4X35G2 devices provide AN1356 1/49 ...
Page 2
... AN1356 - APPLICATION NOTE both ISP and IAP. Keep in mind that IAP can only program the memory sections of the PSD, not the configuration and programmable logic portions. ISP can program all areas of the PSD. The IAP Problem Typically, a host computer downloads firmware into an embedded Flash memory system through a communication channel that is controlled by the MCU ...
Page 3
... In the second design example of this document, you will see how to use the CPLD to implement a loadable counter, a state machine, combinatorial logic, and other functions using OMCs, IMCs, the page register, and external chip-selects. 512 KByte Flash 16-bit 32 KByte Flash MPU/MCU 8KByte SRAM Programmable Logic I/O Channel Embedded System AN1356 - APPLICATION NOTE PSD4x35G2 JTAG ISP System I/O AI04060 3/49 ...
Page 4
... AN1356 - APPLICATION NOTE Figure 3. Top Level Block Diagram of PSD4235G2 PSD4235G2 PHYSICAL CONNECTION Connect your P51XA to the PSD4235G2 as shown in Figure 4. The JTAG programming channel, LCD module, system I/O, MCU I/O signals, and battery back up are optional. They are present in this application note to illustrate PSD functions. ...
Page 5
... ADIO15 _wrl CNTL0 (!WR) _rd P3.7/!RD CNTL1 (!RD) _psen !PSEN CNTL2 (!PSEN) ale PD0 (ALE) PD1 (CLKIN) PD2 (!CSI) _wrh PD3 (!WRH) _reset !RST !RESET AN1356 - APPLICATION NOTE d0-d7 DATA BUS LCD lcd_e MODULE PB0 E lcd_rw PB1 R/W lcd_a0 PB2 RS PB3 PB4 zero PB5 SYSTEM OUTPUTS ...
Page 6
... AN1356 - APPLICATION NOTE FIRST DESIGN EXAMPLE - ISP CAPABLE SYSTEM, LIMITED IAP The first design example is capable of ISP and limited IAP. It outlines the steps required to get a Flash memory P51XA system up and running quickly. The 32 KBytes of PSD secondary Flash memory will be programmed with P51XA firmware (over the JTAG-ISP channel) that will execute low-level system hardware tests. This firmware is also able to access 512 KBytes of main PSD Flash memory, used as data only — ...
Page 7
... PSD 64K bytes PSD 64K bytes PSD nothing mapped rs0, 8k bytes PSD SRAM csiop, PSD cnti regs lcd_e, ext LCD chip sel nothing mapped P51XA-G3 Regs/SRAM AN1356 - APPLICATION NOTE P51XA 8FFFFh fs0 Main Flash 80000h 7FFFFh fs7 Main Flash ...
Page 8
... AN1356 - APPLICATION NOTE Select the secondary PSD Flash memory to reside in Program space upon power-up. The selection of Program space or Data space for the Flash memories determines whether or not the P51XA signals, PSEN or RD respectively, will activate the output enables of the individual PSD Flash memory arrays upon power up ...
Page 9
... In the second design example we use all of the signals shown in the schematic of Figure 4. Define an active-high chip select output on Port B pin pb0. Choose External chip select – Active-HI from the CPLD Output section and name it “lcd_e”. Click Add. AN1356 - APPLICATION NOTE * to these generated ABEL statements, which * ...
Page 10
... AN1356 - APPLICATION NOTE Define a combinatorial CPLD output on Port B pin pb1. Choose Combinatorial from the CPLD Output section and name it “lcd_rw”. Click Add. Define a combinatorial CPLD output on Port B pin pb2. Choose Combinatorial from the CPLD Output section and name it “lcd_a0”. Click Add. ...
Page 11
... Page Register Definition Since 16-bit MCUs have an abundant number of address lines, memory paging is rarely needed for these MCUs. However, the PSD page register bits can be used for logic as well. You will learn how to do this in the second design example. AN1356 - APPLICATION NOTE 11/49 ...
Page 12
... AN1356 - APPLICATION NOTE Figure 9. Page Register Definition For this simple design, click Next >> or click on the “Chip Select Equations” tab. Chip Select Equations (system memory map) Now that the PSD pins are defined, you will need to define the system memory map. This is accomplished by defining all the chip-selects in the system (both internal to the PSD and external chip-selects) ...
Page 13
... Enter its address range as shown: Figure 11. CSIOP Address Range Continue to define internal PSD memory chip-selects for the main Flash memory segments fs0 to fs7, and then secondary Flash memory segments csboot0 to csboot3. Use Figure guide for address ranges. AN1356 - APPLICATION NOTE 13/49 ...
Page 14
... AN1356 - APPLICATION NOTE Again, no signal qualifiers are needed for internal PSD memory chip-selects. Here are a few examples of what the screen should like for these chip-selects: Figure 12. FS0 Address Range Figure 13. FS1 Address Range Figure 14. FS7 Address Range Figure 15. CSBOOT0 Address Range ...
Page 15
... Signal qualifiers may be added by parking the cursor where you want the signal name to go then just double-click on the signal name in the list of ‘Eligible signals’. Figure 17. Signal Qualifiers You can click the View button at any time to see a summary. Once you are satisfied with the results, click the Next >> button. AN1356 - APPLICATION NOTE 15/49 ...
Page 16
... AN1356 - APPLICATION NOTE I/O Logic Equations Now define the two combinatorial output signals “lcd_rw” and “lcd_a0”. You should see the following screen: Figure 18. I/O Logic Equations The signal “lcd_rw” should be a constant 0 volt output, so highlight the signal “lcd_rw” in the ‘List of signals’ ...
Page 17
... If you invoke a process that invalidates other processes downstream, the gray boxes indicate which processes must be invoked again and the red shadow indicates which process to invoke first. The design flow should be in the following state: AN1356 - APPLICATION NOTE 17/49 ...
Page 18
... AN1356 - APPLICATION NOTE Figure 22. Design Flow Additional PSD Settings Click the ‘Additional PSD Settings’ box. This is where you may choose to set the security bit to prevent a device programmer from examining or copying the contents of the PSD. You can also click through the other sheets on this screen to set the JTAG IEEE 1149 ...
Page 19
... PSDsoft Express will extract firmware from that file only between the specified start and stop addresses, and ignore firmware outside of the start and stop addresses. Click on “Merge MCU Firmware” in the main flow diagram and you will see the following: #define statement for each AN1356 - APPLICATION NOTE individual C function within the 19/49 ...
Page 20
... AN1356 - APPLICATION NOTE Figure 23. Merge MCU Firmware In the left column are individual PSD memory segment chip-selects (FS0, FS1, and so on). The next column shows the logic equations for selection of each internal PSD memory segment. These equations reflect the choices that you made while defining PSD internal chip-select equations in an earlier step. In the middle of the screen are hexadecimal start and stop addresses that PSDsoft Express has filled in for you based on your chip-select equations ...
Page 21
... The ST FlashLINK™ JTAG cable, which connects to the PC parallel port. The ST PSDpro device programmer, which also uses the PC parallel port. Third-party programmers, from Stag, BP Micro, and others. See our website at www.st.com for list (PSD Products, Programming, then Programmers). AN1356 - APPLICATION NOTE Scroll to the bottom to get bottom ...
Page 22
... AN1356 - APPLICATION NOTE Programming with FlashLINK™ Connect the FlashLINK™ JTAG-ISP cable to your PC parallel port. Click the ‘JTAG-ISP’ box in the design flow window. You will be asked how many devices are in your JTAG chain. For this example, select ‘Only One’. You would only select ‘More than One’ if you had more than one ISP device in your JTAG chain (even non-ST JTAG devices may be included in the chain). You may choose to disable this question that appears each time you enter the JTAG screen, and then turn it back on later using the ‘ ...
Page 23
... The addresses shown in square brackets in the reportare the direct physical addresses used by a device programmer to access the memory elements of the PSD in a linear fashion (a special device programming mode that the MCU cannot access). AN1356 - APPLICATION NOTE 23/49 ...
Page 24
... AN1356 - APPLICATION NOTE SECOND DESIGN EXAMPLE – ISP, FULL IAP & CPLD LOGIC ELEMENTS This second design example builds upon the first by adding true IAP capability. You will see how to execute from secondary PSD Flash memory in program space while programming the main PSD Flash memory in data space, then move main PSD Flash memory to program space for execution ...
Page 25
... PSD Main Flash 64K bytes PSD Main Flash nothing mapped rs0, 8k bytes PSD SRAM csiop, PSD cnti regs lcd_e, ext LCD chip sel nothing mapped P51XA-G3 Regs/SRAM AN1356 - APPLICATION NOTE P51XA 8FFFFh fs0 80000h 7FFFFh fs7 70000h 6FFFFh fs6 ...
Page 26
... AN1356 - APPLICATION NOTE Figure 28. Memory Map just after P51XA writes 06h to PSD VM register 8FFFFh 64K bytes 80000h 7FFFFh 64K bytes 70000h 6FFFFh 64K bytes 60000h 5FFFFh 64K bytes 50000h 4FFFFh 64K bytes 40000h 3FFFFh 64K bytes 30000h 2FFFFh 64K bytes 20000h ...
Page 27
... You should see the full flow diagram as shown below. This flow also appears if ‘Extended Design Assistant’ is chosen for a new design. Note that the ability to edit the ABEL file is not available for PSD9XXF or PSD4135G devices, both of which have simple PLDs (no registers). Figure 30. Design Flow AN1356 - APPLICATION NOTE Additional box 27/49 ...
Page 28
... AN1356 - APPLICATION NOTE For this second design example, we’ll implement the following logic elements to illustrate PSD functionality: 4-state state machine with comparator feature. Eight debounced inputs used for state machine input. 4-bit reloadable down-counter with initial value set by the MCU. Simple clock divider circuit. ...
Page 29
... Using page register bits saves the use of OMCs.All page register bits are available as CPLD inputs. Note that the page register bits are cleared upon power-up and subsequent resets. Define the “begin” bit as follows, then Click Next >>. AN1356 - APPLICATION NOTE 29/49 ...
Page 30
... AN1356 - APPLICATION NOTE Figure 32. Page Register Definition I/O Logic Equations There are no changes needed to the memory map (chip-selects) from the first design as all IAP enhancements can be accomplished by using the VM register in this case. Click Next >> to skip the ‘Chip Select Equations’ screen. You should see the ‘I/O Logic Equations’ screen as follows: ...
Page 31
... HDL file, so leave them blank. However, define their output enable signals so they are always on by assigning “V ”. That’s all we need click Next >>. CC User-defined Node Equations In this final screen of the Design Assistant, we define internal logic nodes, both combinatorial and registered. Your screen should look like this: AN1356 - APPLICATION NOTE 31/49 ...
Page 32
... AN1356 - APPLICATION NOTE Figure 34. User-defined Node Equations Let’s establish all of the internal nodes used for this second design. They are: Two register nodes for a 4-state state-machine — state_bit_0 and state_bit_1 One register node for a simple clock divider — half_clkin Four register nodes for a down-counter — down_count0 to down_count3 Four register nodes to pre-load the down-counter — ...
Page 33
... You can see that for each register node that is included, its input, clock, reset, and preset values are automatically added to the list. Equations can be specified for all of these elements. Figure 37 illustrates the relationship between a registered node and its signal names for this example. AN1356 - APPLICATION NOTE 33/49 ...
Page 34
... AN1356 - APPLICATION NOTE Figure 37. Internal Register Node and Associated Signal Names state_bit_0 Clock Continue to add nodes. Enter the following node names and node types, clicking Add after each: down_count0 … register down_count1 … register down_count2 … register down_count3 … register init_count0 … register init_count1 … ...
Page 35
... Figure 40. List of Signals Assign the preset for each state machine node to be “Gnd” Figure 41. List of Signals Now lets implement the logic for the simple clock divider circuit shown in Figure 42. Figure 42. Simple Clock Divider half_clkin AN1356 - APPLICATION NOTE GND PRE D Q 1/2 freq of clkin ...
Page 36
... AN1356 - APPLICATION NOTE To do this, make these logic assignments for the registered node, “half_clkin”: half_clkin!half_clkin half_clkin Clockclkin half_clkin ResetGnd half_clkin SetGnd Moving to the down-counter, let’s implement this simple 4-bit auto-reload down-counter, shown in Figure 43. It will be clocked by “half_clkin” and its output “zero” will indicate when the count has reached zero, at which time the counter will automatically reload the initial value and count down again ...
Page 37
... If this WSIPSD PROPERTY statement was not present, then PSDsoft // would pick random MCU bit positions. The WSIPSD PROPERTY is needed // only if the MCU will read or write to MicroCells and only particular MCU data bus position is required by the designer. AN1356 - APPLICATION NOTE 37/49 ...
Page 38
... AN1356 - APPLICATION NOTE WSIPSD PROPERTY ’DataBus_OMC D[3:0]:init_count[3:0]’; // This statement forces the alignment of // init_count bits [3..0] to the MCU data bus bit positions [3..0]. DCOUNT = [down_count3..down_count0]; INIT = [init_count3..init_count0];// 4-bit initial count from MCU STINPUTS = [strobed_in_7..strobed_in_0 inputs that are stobed (sampled) on the way into // the PSD (debounced) ...
Page 39
... PSD as described in the section entitled “Programming the PSD” on page 21. // signal is zero or system is // not ready // stay in this state until pattern ABh is found // stay in this state until pattern CDh is found State 1 if inputs = 'AB' hex AN1356 - APPLICATION NOTE State 3 sequence_ok State inputs = 'CD' hex AI04085 ...
Page 40
... AN1356 - APPLICATION NOTE THIRD DESIGN EXAMPLE – ISP AND ADVANCED IAP The third design example adds enhanced IAP features. The physical connections between the MCU and PSD4235G2 do not change, but chip-selects (memory map) and PSD page register definitions do change. We will not change any of the CPLD logic in this design. ...
Page 41
... IAP loader code gets programmed here by JTAG-ISP or conventional programmer tool. P51XA nothing mapped rs0, 8k bytes PSD SRAM csiop, PSD cnti regs lcd_e, ext LCD chip sel P51XA-G3 Regs/SRAM SWAP bit = 0 VM reg = 12h UNLOCK bit = 0 AN1356 - APPLICATION NOTE (1) P51XA Data Space 8FFFFh fs0 64K bytes PSD Main Flash 80000h 7FFFFh ...
Page 42
... AN1356 - APPLICATION NOTE Figure 46. Memory Map just after P51XA writes 06h to PSD VM register 8FFFFh 64K bytes 80000h 7FFFFh 64K bytes 70000h 6FFFFh 64K bytes 60000h 5FFFFh 64K bytes 50000h 4FFFFh 64K bytes 40000h 3FFFFh 64K bytes 30000h 2FFFFh 64K bytes 20000h ...
Page 43
... Main Flash fs2 64K bytes PSD Main Flash fs1 64K bytes PSD Main Flash fs0 64K bytes PSD Main Flash AN1356 - APPLICATION NOTE P51XA Data Space 8FFFFh nothing mapped 0A000h rs0, 8k bytes PSD SRAM 08000h - 09FFFh csiop, PSD cnti regs 07000h - 070FFh ...
Page 44
... AN1356 - APPLICATION NOTE Figure 48. Memory Map just after P51XA writes 0Ch to PSD VM register 8FFFFh 64K bytes 80000h 7FFFFh 64K bytes 70000h 6FFFFh 64K bytes 60000h 5FFFFh 64K bytes 50000h 4FFFFh 64K bytes 40000h 3FFFFh 64K bytes 30000h 2FFFFh 64K bytes 20000h ...
Page 45
... These internal memory chip-selects must be qualified with the page register bit “swap” as shown below. The secondary PSD memory segments, csboot0 and csboot1, must be additionally qualified by “unlock” AN1356 - APPLICATION NOTE 45/49 ...
Page 46
... AN1356 - APPLICATION NOTE to prevent the MCU from inadvertently writing to IAP boot and loader code after IAP is complete. The following illustrates how the chip-selects will look when you enter their definition based the memory maps of on Figure 45 through to Figure 48. Figure 50. FS0 Address Range Figure 51 ...
Page 47
... P51XA firmware in this file used only for illustration. You will find the pattern AAh in csboot0, and the pattern BBh in csboot1. No firmware filename needs to be designated for the main PSD Flash memory segments (fs0 – fs7) since they will be programmed by the P51XA during IAP. No firmware file needs to AN1356 - APPLICATION NOTE 47/49 ...
Page 48
... AN1356 - APPLICATION NOTE be specified for secondary PSD Flash memory segments csboot2 and csboot3 because these will be used for general purpose data written by the P51XA. Click OK in the merging screen to create a composite object file for programming. You are now ready to program the PSD as described in the section entitled “ ...
Page 49
... Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com/psd apps.psd@st.com (for application support) (for general enquiries) The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES www.st.com AN1356 - APPLICATION NOTE 49/49 ...