IDT72V205L15PF IDT, Integrated Device Technology Inc, IDT72V205L15PF Datasheet - Page 11

• Manufacturer Part Number: IDT72V205L15PF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15PF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 4.5Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 256x18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V205L15PF

NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to V
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
4. In FWFT mode IR goes LOW based on the WCLK edge after Reset.
NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
D
REN, WEN, LD
edge of RCLK and the rising edge of WCLK is less than t
RCLK, WCLK
SKEW1
WCLK
0
RCLK
FL, RXI, WXI
WEN
REN
- D
PAF, WXO/
HF, RXO
FF
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
Q
EF/OR
0
FF/IR
- Q
PAE
RS
17
(2)
(1)
Figure 6. Write Cycle Timing with Single Register-Buffered FF FF FF FF FF (IDT Standard Mode)
t
SKEW1
t
CLKH
(1)
t
WFF
t
t
t
t
RSF
SKEW1
t
RSF
RSF
RSF
t
RSF
RS
t
CLK
, then FF may not change state until the next WCLK edge.
DATA IN VALID
t
RSS
Figure 5. Reset Timing
CONFIGURATION SETTING
t
CLKL
t
DS
t
11
ENS
TM
(2)
t
DH
t
ENH
t
RSR
t
RSR
t
WFF
(4)
OE = 1
OE = 0
CC
COMMERCIAL AND INDUSTRIAL
or GND).
NO OPERATION
(3)
TEMPERATURE RANGES
IDT Standard Mode
IDT Standard Mode
OCTOBER 22, 2008
FWFT Mode
FWFT Mode
4294 drw 06
4294 drw 05