MD1821 Supertex, Inc., MD1821 Datasheet - Page 5

• Manufacturer Part Number: MD1821
• Description: High Speed, Four Channel Mosfet Driver With Inverting Outputs
• Manufacturer: Supertex, Inc.

Timing Diagram
Application Information
For proper operation of the MD1821, low inductance bypass
capacitors should be used on the various supply pins. The
GND pin should be connected to the logic ground. The INA,
INB, INC, IND, and PE pins should be connected to a logic
source with a swing of GND to PE, where PE is 1.8 to 5.0V.
Good trace practices should be followed corresponding to
the desired operating speed. The internal circuitry of the
MD1821 is capable of operating up to 100MHz, with the
primary speed limitation being the loading effects of the load
capacitance. Because of this speed and the high transient
currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible.
Unless the load specifically requires bipolar drive, the VSS
and VL pins should have low inductance feed-through
connections directly to a ground plane. If these voltages
are not zero, then they need bypass capacitors in a manner
similar to the positive power supplies. The power connection
VDD should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to prevent
resonance in the powerleads.
The voltages of VH and VL decide the output signal levels.
These two pins can draw fast transient currents of up to
2.0A, so they should be provided with an appropriate bypass
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capacitor located next to the chip pins. A ceramic capacitor
of up to 1.0µF may be appropriate, with a series ferrite bead
to prevent resonance in the power supply lead coming to
the capacitor. Pay particular attention to minimizing trace
lengths, current loop area and using sufficient trace width to
reduce inductance. Surface mount components are highly
recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small
series resistance in series with the output signal to obtain
better waveform transitions at the load terminals. This will of
course reduce the output voltage slew rate at the terminals
of a capacitive load.
Pay particular attention that parasitic couplings are minimized
from the output to the input signal terminals. The parasitic
feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 1.8V even small coupled
voltages may cause problems. Use of a solid ground plane
and good power and signal layout practices will prevent this
problem. Be careful that a circulating ground return current
from a capacitive load cannot react with common inductance
to cause noise voltages in the input logic circuitry.
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MD1821