IDT72V235L20PF IDT, Integrated Device Technology Inc, IDT72V235L20PF Datasheet - Page 21

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IDT72V235L20PF

Manufacturer Part Number
IDT72V235L20PF
Description
IC FIFO SYNC 2048X18 20NS 64TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V235L20PF

Function
Synchronous
Memory Size
36.8K (2K x 18)
Data Rate
50MHz
Access Time
20ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V235L20PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V235L20PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V235L20PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
NOTES:
1. t
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
D
D
WCLK
Q
RCLK
edge of WCLK and the rising edge of RCLK is less than t
the rising edge of RCLK is less than t
SKEW1
SKEW1
0
WEN
0
0
REN
0
-
-
WCLK
Q
RCLK
OE
D
-
EF
-
WEN
REN
17
17
Q
D
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus t
OR
is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and
17
17
t
ENS
t
DS
t
t
OLZ
ENS
Figure 27. OR
Figure 26. Read Cycle Timing with Double Register-Buffered EF EF EF EF EF (IDT Standard Timing)
W
t
ENH
1
DATA IN OUTPUT REGISTER
t
SKEW1
A
t
REF
OR
OR
OR
OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
t
OE
, then the OR deassertion may be delayed one extra RCLK cycle.
t
DH
t
FIRST WORD
t
ENH
t
ENS
t
DS
SKEW1
1
W
SKEW1
2
(1)
t
. then the EF deassertion may be delayed an extra RCLK cycle.
SKEW1
t
(1)
t
DH
ENH
1
2
W
3
21
LAST WORD
TM
NO OPERATION
3
W
t
4
t
REF
A
t
DS
t
OHZ
2
t
REF
W
t
CLKH
[n +2]
COMMERCIAL AND INDUSTRIAL
t
REF
W
1
TEMPERATURE RANGES
REF
t
CLK
. If the time between the rising
OCTOBER 22, 2008
W
t
CLKL
[n+3]
4294 drw 26
4294 drw 27

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