SSD1322 SOLOMON SYSTECH, SSD1322 Datasheet
SSD1322
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SSD1322 Summary of contents
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... Segment/Common Driver with Controller This document contains information on a product under development. Solomon Systech reserves the right to change or discontinue this product without notice. http://www.solomon-systech.com SSD1322 Rev 0.10 SSD1322 Product Preview Copyright 2008 Solomon Systech Limited P 1/56 Apr 2008 Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Set Second Pre-charge period (B6h)...........................................................................................................44 10.1.18 Set Gray Scale Table (B8h).........................................................................................................................44 10.1.19 Select Default Linear Gray Scale Table (B9h)............................................................................................44 10.1.20 Set Pre-charge voltage (BBh) .....................................................................................................................44 10.1.21 Set V Voltage (BEh).............................................................................................................................44 COMH 10.1.22 Set Contrast Current (C1h).........................................................................................................................44 10.1.23 Master Current Control (C7h) ....................................................................................................................45 SSD1322 Rev 0.10 ............................................................................................................................12 ............................................................................................................................................22 G ....................................................................................................................22 ENERATOR B .................................................................................................................................23 LOCK .............................................................................................................................................24 .........................................................................................................................................28 ...........................................................................................................................29 SEQUENCE ..............................................................................................................................................30 ...
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... Set Multiplex Ratio (CAh) ...........................................................................................................................45 10.1.25 Set Command Lock (FDh)...........................................................................................................................45 11 MAXIMUM RATINGS........................................................................................................ CHARACTERISTICS................................................................................................... CHARACTERISTICS................................................................................................... 48 14 APPLICATION EXAMPLES ............................................................................................. 53 15 PACKAGE INFORMATION.............................................................................................. 55 15.1 SSD1322UR1 DETAIL DIMENSION SSD1322 Rev 0.10 ...................................................................................................................55 P 3/56 Apr 2008 Solomon Systech Datasheet pdf - http://www.DataSheet4U.net/ ...
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... TABLES T 3 ABLE RDERING NFORMATION T 5-1: SSD1322Z B ABLE UMP T 6-1: SSD1322UR1 P ABLE T 7-1: SSD1352 P D ABLE ABLE US NTERFACE SELECTION T 8-1 : MCU ABLE INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE T 8 ABLE ONTROL PINS ABLE ONTROL PINS ABLE ONTROL PINS OF T 8-5: C ...
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... FIGURES F 4-1 : SSD1322 B IGURE LOCK F 5-1: SSD1322Z D IGURE IE F 5-2: SSD1322Z IGURE ALIGNMENT MARK DIMENSION F 6-1: SSD1322UR1 P IGURE F 8 IGURE ATA READ BACK PROCEDURE F 8 IGURE XAMPLE IGURE XAMPLE IGURE ISPLAY DATA READ BACK PROCEDURE F 8 IGURE RITE PROCEDURE IN F 8-6: W IGURE ...
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... It consists of 480 segments and 128 commons. This IC is designed for Common Cathode type OLED/PLED panel. SSD1322 displays data directly from its internal 480 x 128 x 4 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through the hardware selectable 6800-/8080-series compatible Parallel Interface or Serial Peripheral Interface ...
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... BLOCK DIAGRAM V BGGND RES# CS# D/C# R/W# (WR#) E(RD#) BS0 BS1 DDIO DD1 LSS V SL GPIO0 GPIO1 SSD1322 Rev 0.10 Figure 4-1 : SSD1322 Block Diagram CI Regulator DD P 7/56 Apr 2008 . . COM126 . COM124 . . | . | . . COM2 . COM0 . . . . SEG0 . SEG1 . . | . | . . SEG478 . SEG479 . . . ...
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... Alignment mark + shape (5583.95,200.78) + shape (-5634.61,-309.88) SSL Logo (-5682.11,-258.98) (For details dimension please see Figure 5-2) SSD1322Z Pad 1,2,3,…->728 Gold Bumps face up Figure 5-2: SSD1322Z alignment mark dimension Center: (-5364.61, -309.88 µm 2 Size: P 8/56 Apr 2008 12 1.53 mm ...
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... CL -1795.06 -654.15 77 VSS -1703.06 -654.15 78 DOF# -1611.06 -654. -1521.06 -654.15 80 VSS -1451.06 -654.15 SSD1322 Rev 0.10 Table 5-1: SSD1322Z Bump Die Pad Coordinates Pad no. Pin name X-pos Y-pos Pad no. 81 RES# -1381.06 -654.15 161 82 CS# -1311.06 -654.15 162 83 D/C# -1241.06 -654.15 163 84 VSS -1171 ...
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... SEG177 1625 687.81 397 SEG178 1600 687.81 398 SEG179 1575 687.81 399 SEG180 1550 687.81 400 SEG181 1525 687.81 SSD1322 Rev 0.10 Pad no. Pin name X-pos Y-pos Pad no. 401 SEG182 1500 687.81 481 402 SEG183 1475 687.81 482 403 SEG184 1450 687 ...
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... COM72 -6092.34 -242.15 717 COM73 -6092.34 -277.15 718 COM74 -6092.34 -312.15 719 COM75 -6092.34 -347.15 720 COM76 -6092.34 -382.15 SSD1322 Rev 0.10 Pad no. Pin name X-pos Y-pos 721 COM77 -6092.34 -417.15 722 COM78 -6092.34 -452.15 723 COM79 -6092.34 -487.15 724 COM80 -6092 ...
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... PIN ARRANGEMENT 6.1 SSD1322UR1 pin assignment Note: (1) COM sequence is listed in terms of dual COM mode; refer to Table 9-1 for details. SSD1322 Rev 0.10 Figure 6-1: SSD1322UR1 Pin Assignment P 12/56 Apr 2008 Solomon Systech Datasheet pdf - http://www.DataSheet4U.net/ ...
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... COMB21 155 76 COMB20 156 77 COMB19 157 78 COMB18 158 79 COMB17 159 80 COMB16 160 SSD1322 Rev 0.10 Table 6-1: SSD1322UR1 Pin Assignment Table Pin name Pad no. Pin name Pad no. COMB15 161 SEG206 241 COMB14 162 SEG205 242 COMB13 163 SEG204 243 COMB12 164 SEG203 244 ...
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... BGGND P GPIO0 IO GPIO1 BS[1:0] I SSD1322 Rev 0. Not Connected Pull LOW= connect to Ground Table 7-1: SSD1352 Pin Description Power supply pin for core logic operation. A capacitor is required to connect between V this pin and . SS Refer to Section 8.10 for details. Power supply for interface logic level. It should be matched with the MCU interface voltage level ...
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... I E (RD#) I D[7:0] IO DN[9:0] IO SSD1322 Rev 0.10 This pin is the segment output current reference pin. A resistor should be connected between this pin and V around 10uA. Please refer to section 8.6 for the formula of resistor value from I This pin must be connected to V DDIO External clock input pin. ...
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... DOF# O SEG[479:0] O COM[127:0] O SSD1322 Rev 0.10 This pin is No Connection pins. Nothing should be connected to this pin. This pin should be left open individually. This pin is No Connection pins. Nothing should be connected to this pin. This pin should be left open individually. These pins provide the OLED segment driving signals. These pins are V display is OFF ...
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... FUNCTIONAL BLOCK DESCRIPTIONS 8.1 MCU Interface SSD1322 MCU interface consist of 8 data pin and 5 control pins. The pin assignment at different interface mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[1:0] pins (refer to for BS[1:0] pins setting) Table 7-2 Table 8-1 : MCU interface assignment under different bus interface mode ...
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... Figure 8-2 : Example of Write procedure in 8080 parallel interface mode CS# WR# D[7:0] D/C# high RD# low Figure 8-3 : Example of Read procedure in 8080 parallel interface mode CS# RD# D[7:0] D/C# high WR# low SSD1322 Rev 0. Dummy read Read 1st data P 18/56 Apr 2008 n+1 n+2 Read 2nd data Read 3rd data Solomon Systech Datasheet pdf - http://www.DataSheet4U.net/ ...
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... SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM) or command register in the same clock. SSD1322 Rev 0.10 Table 8-3 : Control pins of 8080 interface (Form 1) ...
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... Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0). Under serial mode, only write operations are allowed. Function Write command Write data CS# SDIN/ DB1 SCLK SCLK (D0) D/C# SDIN(D1) SSD1322 Rev 0.10 Figure 8-5 : Write procedure in 4-wire Serial interface mode DB2 DBn Table 8-5: Control pins of 3-wire Serial interface E(RD#) R/W#(WR#) CS# ...
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... D30241[3:0] D30241[7:4] D30240[3:0] D30240[7:4] COM127 7F D30481[3:0] D30481[7:4] D30480[3:0] D30480[7:4] RAM COM Row Outputs Address (HEX) 8.3.2 Data bus to RAM mapping Read / Write Data Bus width 8 bits SSD1322 Rev 0.10 Table 8-6 : GDDRAM in Gray Scale mode (RESET) SEG1 SEG2 SEG3 00 D1[7:4] D0[3:0] D0[7:4] D241[7:4] D240[3:0] D240[7:4] | Corresponding to one pixel ...
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... It can be changed by command B3h A[7:4]. The higher the register setting osc results in higher frequency. If the frame frequency is set too low, flickering may occur. On the other hand, higher frame frequency leads to higher power consumption on the whole system. SSD1322 Rev 0.10 Figure 8-7 : Oscillator Circuit Internal Oscillator ...
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... REF R1 = (Voltage (18 – 10uA ≈ 1.2M SSD1322 Rev 0.10 * scale factor *2 REF = 300uA at maximum contrast 255, I SEG = 10uA Figure 8 Current Setting by Resistor Value REF SSD1322 I (voltage at REF ≈ 10uA I REF this pin = V – pin is V – 6V, the value of resistor R1 can be found as below: ...
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... The block diagrams and waveforms of the segment and common driver are shown as follow. Figure 8-9 : Segment and Common Driver Block Diagram – Single COM mode V COMH Non-selected Row Selected Row Common Driver SSD1322 Rev 0.10 OLED Pixel V LSS P 24/56 Apr 2008 ...
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... In the scanned row, the pixels on the row will be turned ON or OFF by sending the corresponding data signal to the segment pins. If the pixel is turned OFF, the segment current is kept the other hand, the segment drives to I when the pixel is turned ON. SEG SSD1322 Rev 0.10 OLED Pixel V ...
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... There are four phases to driving an OLED a pixel. In phase 1, the pixel is reset by the segment driver order to discharge the previous data charge stored in the parasitic capacitance along the segment electrode. The period of phase 1 can be p requires a longer period for discharging. SSD1322 Rev 0.10 Figure 8-11 : Segment and Common Driver Signal Waveform Non - selected Row ...
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... OLED panel. The length of phase 4 is defined by command B8h or B9h. In the table, the gray scale is defined in incremental way, with reference to the length of previous table entry. SSD1322 Rev 0.10 can be programmed by the command BBh. The period of phase 2 can be ...
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... Figure 8-13 : Relation between GDDRAM content and Gray Scale table entry (under command B9h Enable GDDRAM data (4 bits) 0000 0001 0010 0011 : : 1101 1110 1111 Note: (1) Both GS0 and GS1 have no 2 charge (phase 2). SSD1322 Rev 0.10 Linear Gray Scale Table) Gray Scale Table GS0 (1) GS1 GS2 GS3 : : GS13 GS14 GS15 nd ...
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... Power ON and OFF sequence The following figures illustrate the recommended power ON and power OFF sequence of SSD1322 (assume V and V are at the same voltage level and internal V CI DDIO Power ON sequence: 1. Power CI, 2. After DDIO set RES# pin LOW (logic low) for at least 100us (t 3 ...
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... V Regulator DD In SSD1322, the power supply pin for core logic operation, V internally regulated through the V The internal V regulator is enabled by setting bit A[ command ABh “Function Selection” should be larger than 2.6V when using the internal should be notice that, no matter V ...
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... A[7: B[ A[6: SSD1322 Rev 0.10 Table 9-1 : Command table Command Enable Gray Scale table Set Column Address ...
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... A[ AE~ A[7: SSD1322 Rev 0. Command Set Display Offset Set Display Mode ...
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... A14[7:0] A14 A14 A14 A14 A15[7:0] A15 A15 A15 A15 SSD1322 Rev 0. Command Set Front Clock Divider / Oscillator Frequency Set GPIO ...
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... A[6: A[ Note (1) “*” stands for “Don’t care”. SSD1322 Rev 0. Command Select Default Linear Gray Scale table Set Pre-charge voltage ...
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... RAM. 10.1.4 Read RAM Command (5Dh) After entering this single byte command, data is read from display RAM until another command is written. Address pointer is increased accordingly. This command must be sent before read data from RAM. SSD1322 Rev 0.10 P 35/56 Apr 2008 Solomon Systech Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Figure 10-110-2 : Example of Column and Row Address Pointer Movement (Gray Scale Mode) 0 Row 0 Row 1 Row Row 125 Row 126 Row 127 SSD1322 Rev 0.10 ). While the end row 126 and end column 118 RAM location is accessed, the 1 ... : : : P 36/56 Apr 2008 118 119 ...
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... A[ (reset): RAM Column 0 ~ 119 maps to SEG0-SEG3 ~ SEG476-SEG479 A[ RAM Column 0 ~ 119 maps to SEG476-SEG479 ~ SEG0-SEG3 • Nibble Remap (A[2]) A[ (reset): Data bits direct mapping is performed A[ The four nibbles of the data bus for RAM access are re-mapped The effects are demonstrated in SSD1322 Rev 0.10 Col 0 Col 1 ….. : : ...
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... COM127 COM126...COM 65 COM64...SEG479...SEG0...COM0 COM1...COM62 COM63 A[ Enable COM split odd even, pin assignment of common is in odd even split as COM127 COM125...COM3 COM1...SEG479...SEG0...COM0 COM2...COM124 COM126 Details of pin arrangement can be found in Figure 10-6. SSD1322 Rev 0. ...
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... Pad 1,2,3,… Gold Bumps face up P 39/56 Apr 2008 Figure 10-6 Figure 10-7 Case 2 A[5] =1 B[4]=0 Disable Dual COM mode ROW126 480 x 128 ROW2 ROW1 ROW0 COM0 SSD1322Z COM64 COM1 COM126 COM127 COM63 Pad 1,2,3,… Gold Bumps face up B[4]=1 ROW63 ROW62 ROW1 ROW0 COM0 COM1 COM62 Solomon Systech Datasheet pdf - http://www ...
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... COM88 ROW88 COM89 ROW89 COM90 ROW90 COM91 ROW91 : : : : COM124 ROW124 COM125 ROW125 COM126 ROW126 COM127 ROW127 Display Example SSD1322 Rev 0.10 shows an example of using this command when Figure 10-8 Display Start Line (A1h) Display Start Line (A1h ROW40 ROW0 ROW41 ROW1 ROW42 ROW2 ...
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... COM88 ROW88 COM89 ROW89 COM90 ROW90 COM91 ROW91 : : : : COM124 ROW124 COM125 ROW125 COM126 ROW126 COM127 ROW127 Display Example SSD1322 Rev 0.10 Figure 10-9 : Example of Set Display Offset with no Remap Display Offset (A2h)=40 Display Offset (A2h)=0 ROW40 ROW0 ROW41 ROW1 ROW42 ROW2 ROW43 ROW3 : : ...
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... RAM as shown in Figure. • Inverse Display (A7h) The gray level of display data are swapped such that “GS0” ↔ “GS15”, “GS1” ↔ “GS14”, … Figure 10-13 shows an example of inverse display. SSD1322 Rev 0.10 Figure 10-10 : Example of Normal Display GDDRAM . Figure 10-11 : Example of Entire Display ON ...
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... Program the oscillator frequency Fosc which is the source of CLK if CLS pin is pulled HIGH. The 4- bit value results in 16 different frequency settings being available. 10.1.16 Set GPIO (B5h) This double byte command is used to set the states of GPIO0 and GPIO1 pins. Refer to SSD1322 Rev 0.10 Figure 10-14 : Example of Partial Mode Display GDDRAM ...
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... This double byte command sets the high voltage level of common pins, V programmed with reference to V 10.1.22Set Contrast Current (C1h) This double byte command is used to set Contrast Setting of the display. The chip has 256 contrast steps from 00h to FFh. The segment output current I brighter display. SSD1322 Rev 0.10 Figure 10-15 Brightness Panel response Gamma Setting ...
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... Entering FDh 12h (A[2]=0b) can unlock the OLED driver IC. That means the driver IC resume from the “Lock” state. And the driver IC will then respond to the command and memory access. SSD1322 Rev 0.10 and Figure 10-9 show examples of setting the multiplex ratio through command ...
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... Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description. *This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. SSD1322 Rev 0.10 Table 11-1 : Maximum Ratings ) ...
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... Supply Current CC CC Segment Output Current I Setting SEG V =18V, I =10uA CC REF Segment output current Dev uniformity Adjacent pin output Adj. Dev current uniformity (contrast = FF) SSD1322 Rev 0. must be larger than or equal Table 12 Characteristics Test Condition - - Iout = 100uA Iout = 100uA - - =2.8V, V =OFF CI ...
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... B3h A[7:4] is OSC in default value. (2) D: divide ratio K: Phase 1 period + Phase 2 period + X X: DCLKs in current drive period. Default 122 = 138 SSD1322 Rev 0.10 SS Table 13 Characteristics Test Condition V = 2.5V DD ...
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... Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) PW CSH Chip Select High Pulse Width (write) t Rise Time R t Fall Time F Figure 13-1 : 6800-series MCU parallel interface characteristics D/C # R/W#(WR#) # E(RD#) CS D[7:0] (WRITE) D[7:0] (READ) SSD1322 Rev 0.10 V =1.6V, = 3.3V 25°C) CI DDIO CSL DSW Valid Data t ACC ...
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... Chip select setup time CS t Chip select hold time to read signal CSH t Chip select hold time CSF Figure 13-2 : 8080-series MCU parallel interface characteristics Write cycle CS D/ R/W#(WR#) PWLW D[7:0] SSD1322 Rev 0.10 V =1.6V, = 3.3V 25°C) CI DDIO A Parameter t CSF cycle t PWHW t t ...
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... Clock Low Time CLKL t Clock High Time CLKH t Rise Time R t Fall Time F D/C# CS# SCLK (D0 SDIN (D1) CS# SCLK (D0) SDIN(D1) SSD1322 Rev 0.10 V =1.6V, = 3.3V 25°C) CI DDIO A Figure 13-3 : Serial interface characteristics (4-wire SPI CSS t CLKL t DSW Valid Data 51/56 Apr 2008 ...
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... CLKL t Clock High Time CLKH t Rise Time R t Fall Time F CS# SCLK (D0 SDIN (D1) CS# SCLK (D0) SDIN D/C# D7 (D1) SSD1322 Rev 0.10 V =1.6V, = 3.3V 25°C) CI DDIO A Figure 13-4: Serial interface characteristics (3-wire SPI) t CSS t CYCLE t CLKL t DSW Valid Data 52/56 Apr 2008 Min Typ ...
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... APPLICATION EXAMPLES Figure 14-1 : SSD1322 application example for 8-bit 6800-parallel interface mode (Internal regulated V The configuration for 8-bit 6800-parallel interface mode, externally V (V =3.3V (V must be > 2.6V), Internal regulated 18V V CC Voltage – 6V. For V REF (Voltage REF 10u = 1.2MΩ ...
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... Figure 14-2 : SSD1322 application example for 8-bit 6800-parallel interface, dual COM mode (Internal V The configuration for 8-bit 6800-parallel interface mode, externally V (V =3.3V (V must be > 2.6V), Internal regulated 18V V CC Voltage – 6V. For V REF (Voltage REF 10u = 1.2MΩ ...
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... PACKAGE INFORMATION 15.1 SSD1322UR1 detail dimension SSD1322 Rev 0.10 Figure 15-1: SSD1322UR1 Detail Dimension P 55/56 Apr 2008 Solomon Systech Datasheet pdf - http://www.DataSheet4U.net/ ...
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... Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with control Marking Symbol . Hazardous Substances test report is available upon requested. http://www.solomon-systech.com SSD1322 Rev 0.10 P 56/56 Apr 2008 Solomon Systech ...