SSD1809 Solomon Systech, SSD1809 Datasheet
SSD1809
Related parts for SSD1809
SSD1809 Summary of contents
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... SEMICONDUCTOR TECHNICAL DATA LCD Segment / Common Driver With Controller CMOS SSD1809 is a single-chip CMOS LCD driver with controller for liquid crystal dot-matrix graphic display system. It consists of 225 high voltage driving output pins for driving 160 Segments, 64 Commons and 1icon driv- www.DataSheet4U.com ing-Common ...
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... OSC1 Display Timing Generator OSC2 CE RES SSD1809 REV1.3 03/02 2 Block Diagram COM0 ~ COM64 SEG0 ~ SEG159 HV Buffer Cell Level Shifter 65 Bit 160 Bit Latch Latch GDDRAM 65x 160 Bits Control Logic Command Decoder Command/Data Interface P/S 68/80 D/C CLK / Level Selector V LL2 V CC ...
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... In the TAB package, pin1(VDC) & pin2(DVDD) are connected to DVDD. Pin46(AVDD), pin47(P/S) & pin48(68/80) are connected to AVDD. SOLOMON SSD1809T PIN ASSIGNMENT (COPPER VIEW) ENCAPSULANT DIE Normal Design TAB * COPPER POLYIMIDE SSD1809 REV 1.3 03/02 3 ...
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... SSD1809T Pin Assignment Table TAB Signal Name Pin # RES 4 D CLK/ WR/SCK SDA www.DataSheet4U.com ...
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... This device is not radiation protected. =25°C; unless otherwise specified.) A Min Typ ) 2.2 3.0 SS 2 170 - - - 0.9 voltage depends Floating -5 - REV 1.3 03/02 . Reliability D D Max Unit 3.5 V 3.5 V 3.5 V 450 A 270 16 0.1 -0 SSD1809 5 ...
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... Input Capacitance IN (OSC1, OSC2, all logic pins) Temperature Coefficient Compensation* PTC0 Flat Temperature Coefficient PTC3 Temperature Coefficient 3* *The formula for the temperature coefficient (TC) is 50° 0° TC(%)= X 50°C - 0°C SSD1809 REV1.3 03/ =2.2 to 3.5V Test Condition - ...
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... Fosc / [96 x (Frame Freq Register + 1)] Fosc / [144 x (Frame Freq Register + 1)] Fosc / [96 x (Frame Freq Register +1)] Fosc / [128 x (Frame Freq Register + 1)] Fosc / [192 x (Frame Freq Register + 1)] Fosc / [288 x (Frame Freq Register + 1)] within oper- See Figure 1 for the relationship 1.5M 2. Max Unit - kHz SSD1809 REV 1.3 03/02 7 ...
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... DHW t Data Delay Time for Read Cycle DD t Data Hold Time for Read Cycle DHR www.DataSheet4U.com D -D (Write Cycle (Read Cycle SSD1809 REV1.3 03/02 8 CLK t AS R/W D/C CE Figure 2 : Timing Characteristics for 6800-Series Parallel Interface o =- =2.2 to 3.5V, V =0V ...
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... Cycle SOLOMON =- cycle t AS D/C CE Figure 3 : Timing Characteristics for 80-Series Parallel Interface =2.2 to 3.5V, V =0V Min Typ Max Unit 1000 - - ns - 500 - ns - 200 - ns - 250 - ns - 350 - ns - 250 - ns - 350 - ns - 100 - DHR D D SSD1809 REV 1.3 03/02 9 ...
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... Enable Pulse Width EH t Address Setup Time AS t Address Hold Time AH t Data Setup Time DS t Data Hold Time DH t Enable Lead Time LEAD t Enable Lag Time LAG www.DataSheet4U.com SCK D/C SDA CE SSD1809 REV1.3 03/ Min 1000 - - - - - - - t cycle LEAD ...
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... DV Power is supplied to the digital control circuit and DC/DC converter of the driver using these two pins Remark: In SSD1809T TAB package, V and P/S pin & 68/80 pin are connected to AV interface can be used and DV verter in this package LL2 Group of voltage level pins for driving the LCD panel. They can either If the internal bias voltage levels generator is enabled required on each pin ...
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... Row 0 Page 1 Page 2 Page 8 Row 63 Row 64 Page 9 Note : The configuration in parentheses represent the remapping of Rows and Columns SSD1809 REV1.3 03/02 12 OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER Description of Block Diagram Module MPU Serial Peripheral Interface The serial interface consists of serial clock SCK, serial data SDA, D/C, and CE ...
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... M signal. This module chip low power RC oscillator circuitry (Fig- The oscillator frequency can be selected in the range of Oscillator enable enable Buffer SSD1809 External component COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Figure 7a : LCD Display Example “0” SSD1809 REV 1.3 03/02 13 ...
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... COM0 COM1 www.DataSheet4U.com SEG0 SEG1 M SEG0-COM0 Non-selected Pixel SEG0-COM1 Selected Pixel SSD1809 REV1.3 03/02 14 TIME SLOT Figure 7b : LCD Driving Signal from SSD1809 TIME SLOT Figure 7c : Effective LCD waveform on LCD pixel LL6 V LL5 V LL4 V LL3 V LL2 V SS ...
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... This command is used to enable the internal Voltage Generator to generate the V from pins cannot have external bias voltage sup- LL whereas off-pixels by 0.58xV . DD DD whereas off-pixels by 0.5xV . DD DD whereas off-pixels by 0.41xV . DD DD whereas off-pixels by 0.33xV . Disable the voltage generator if external DD SSD1809 REV 1.3 03/02 15 ...
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... Mux from 2 Mux to 65 Mux or the Chinese character display mode with different character line from 1 line to 3 lines. Figure 8a & the section “Display Output Description” show the 65 Mux Graphic display mode and 3-line Chinese character display mode respectively. SSD1809 REV1.3 03/02 16 ...
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... Set display rows location at 06h shown in Figure 8h. Figure 8e: Vertical scrolling with writing 07h to scrolling register Figure 8f: Disable row re-mapping & column re-mapping and Rewrite map content. Figure 8g: Vertical scrolling with writing 3Eh to scrolling register Figure 8h: Centering with display rows locatiion 06h SSD1809 REV 1.3 03/02 17 ...
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... Voltage Generator Enable 0 0010110X Voltage Regulator Enable 0 0010111X Voltage Divider Enable 0 0011000X Internal Contrast Control Enable 0 0011001X Set Display Frequency 0 0011010X Save/Restore GDDRAM Column 0 Address SSD1809 REV1.3 03/02 18 Comment Set GDDRAM Page Address using =0000 : page 1 (POR) 3 ...
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... Mux) (POR Don’ t care 16-Point Chinese Character Mode character row (17 Mux character rows (35 Mux character rows (53 Mux Don’ t care SSD1809 REV 1.3 03/02 19 ...
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... Reserved 0 0111111X Set Oscillator Enable Set GDDRAM Column Address SSD1809 REV1.3 03/02 20 Comment Next command (byte will be written to the Frame Fre quency Register 0000 : Frame Frequency Register = ...
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... (0010011X )* 0 ( (0011010X ) 0 (00110110 (00001001)* (00110111 SSD1809 REV 1.3 03/02 21 ...
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... RES , CLK/WR/SCK, R/ W/RD, CE and D/C should known state. SSD1809 REV1.3 03/ DUM1 DUM2 DUM3 DUM4 SS SS LL2 LL3 68/80 CE SSD1809 R D/C SDA OSC2 OSC1 560pF 500k 900k can be left open for Regulator disable and Contrast Disable ...
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... 500k 560pF 900k 4.7 F can be left open for Regulator disable and Contrast Disable 0 LL4 LL5 LL6 CC COM0 to COM64 SEG0 to SEG159 0.1 F 0.1 F REV 1.3 03/02 To LCD Panel SSD1809 23 ...
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... REV1.3 03/ DUM1 DUM2 DUM3 DUM4 SS SS LL2 LL3 P/S 68 SSD1809 RES R D/C SDA OSC2 OSC1 560pF 500k 900k and V can be left open for Regulator disable and Contrast Disable. ...
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... SOLOMON PACKAGE DIMENSIONS SSD1809T TAB PACKAGE DIMENSION - 1 SSD1809 REV 1.3 03/02 25 ...
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... SSD1809 REV1.3 03/02 26 PACKAGE DIMENSIONS SSD1809T TAB PACKAGE DIMENSION - 2 SOLOMON ...
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... Solomon Systech was negligent regarding the design or manufacture of the part. SSD1809 ...