SSD1809 Solomon Systech, SSD1809 Datasheet - Page 13

• Manufacturer Part Number: SSD1809
• Description: LCD SEGMENT / COMMON DRIVER
• Manufacturer: Solomon Systech

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SOLOMON
Graphic Display Data RAM (GDDRAM)
to be displayed. The size of the RAM is determined by number of
row times the number of column (160x65 = 10400 bits). Figure 5 is a
description of the GDDRAM address map. For mechanical flexibility,
re-mapping on both Segment and Common outputs are provided.
LCD Driving Voltage Generator and Regulator
It takes a single supply input and generate necessary bias voltages.
It consists of :
2. Voltage Regulator
3. Voltage Divider
4. Self adjust temperature compensation circuitry
5. Contrast Control Block
1. 2X, 3X, 4X and 5X DC-DC Converter
The GDDRAM is a bit mapped static RAM holding the bit pattern
This module generates the LCD voltage needed for display output.
To generate the V
used for LCD panel which needs lower driving voltage for less
power consumption. 5X DC-DC converter is used for LCD panel
which needs higher driving voltage.
Feedback gain control for initial LCD voltage. it can also be used
with external contrast control.
Divide the LCD display voltage (V
put. This is a low power consumption circuit which can save the
most display current compare with
method.
Provide 2 different compensation grade selections to satisfy the
various liquid crystal temperature grades. The grading can be
selected by software control.
Software control of 16 voltage levels of LCD voltage.
All blocks can be individually turned off if external voltage genera-
tor is employed.
CC
voltage. 2X, 3X and 4X DC-DC converter are
Internal Oscillator selected
LL2
-V
traditional
OSC1
LL6
) from the regulator out-
Feedback for internal oscillator
For external CLK input
enable1
Oscillation Circuit
resistor
Figure 6 : Oscillator Circuitry
enable2
ladder
OSC2
Display Timing Generator
ure 6).
25kHz to 200kHz by external resistor. One can enable the circuitry
by software command. For external clock provided, feed the clock to
OSC2 and leave OSC1 open.
65 Bit Latch / 160 Bit Latch
First 65 bits are Common driving signals and other 160 bits are Seg-
ment driving signals. Data will be input to the HV-buffer Cell for
bumping up to the required level.
Level Selector
voltage can be separated into two sets and used with different
cycles. Synchronization is important since it selects the required LCD
voltage level to the HV Buffer Cell for output signal voltage pump.
HV Buffer Cell (Level Shifter)
voltage output signal to the required driving voltage. The output is
shifted out with an internal FRM clock which comes from the Display
Timing Generator. The voltage levels are given by the level selector
which is synchronized with the internal M signal.
A 225 bit long register which carries the display signal information.
Level Selector is a control of the display synchronization. Display
HV Buffer Cell works as a level shifter which translates the low
This module is an on chip low power RC oscillator circuitry (Fig-
The oscillator frequency can be selected in the range of
External component
enable
Buffer
Figure 7a : LCD Display Example “0”
Oscillator enable
SSD1809
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
REV 1.3
03/02
SSD1809
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