SSD1730 Solomon, SSD1730 Datasheet - Page 16

• Manufacturer Part Number: SSD1730
• Description: SSD1730 MLA Power Chip CMOS
• Manufacturer: Solomon

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VDD_PWR
Clock Signal Generator
This circuit generates the clock for charge pump circuit from the pulse signal LP. When the display off control signal
XSLP is set to VSS, the clock will stop and the voltage converter will halt. The signal clocks AB and XBB for the
column driver voltage generator and the row driver voltage generator are also generated by this circuit.
Output Signal XBB
Driver Voltage Generator
This circuit generates all voltage levels which are required to drive both the row driver and the column driver. The
voltage converter circuit comprises a CMOS charge pump-type DC/DC converter which is formed by five individual
voltage generator circuits including 1) Column driver voltage generator, 2) Row driver voltage conversion circuit, 3)
VDD_ROW voltage generator circuit, 4) +V1 voltage generator circuit and 5) External contrast control circuit. Figure
8 shows the relationship between these voltage generator circuits and Table 14 summarized all logical formulas
which can be used to calculated these voltage levels. Besides, in order to generate these voltages, external
capacitors for the charge pump are necessary. Application circuit shows their connections
Input Signal XSLP
SOLOMON
Output Signal AB
Input Signal LP
VSS
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Row driver
voltage
conversion
circuit
Figure 7 - Timing diagram for LP, AB and XBB
Figure 8 - Voltage generator control circuit
Row driver voltage generator
-V3B
VEM
VDD_ROW voltage
Ext. contrast
control circuit
generator circuit
Column driver
+V1 voltage generator
generator
voltage
Rev 2.0
04/2002
circuit
SSD1730
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V3
V2
VC
-V2
-V3
VDD_ROW
+V1
VEE
-V1
14
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