MCP40D17 Microchip Technology Inc., MCP40D17 Datasheet - Page 34

• Manufacturer Part Number: MCP40D17
• Description: 7-bit Single I 2 C? With Command Code Digital Pot With Volatile Memory In Sc70
• Manufacturer: Microchip Technology Inc.

MCP40D17/18/19
5.2
I
•
•
•
•
•
•
Figure 5-8
5.2.1
The Start bit (see
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 5-2:
5.2.2
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see
FIGURE 5-3:
5.2.3
The A bit (see
device to the Master device. Depending on the context
of the transfer sequence, the A bit may indicate
different things. Typically the Slave device will supply
an A response after the Start bit and 8 “data” bits have
been received. The A bit will have the SDA signal low.
FIGURE 5-4:
DS22152B-page 34
2
C bit definitions include:
SDA
SCL
SDA
SCL
Start Bit
Data Bit
Acknowledge (A) Bit
Repeated Start Bit
Stop Bit
Clock Stretching
SDA
SCL
I
2
S
S
shows the waveform for these states.
C Bit Definitions
START BIT
DATA BIT
ACKNOWLEDGE (A) BIT
Figure
8
Figure
D0
5-4) is a response from the Slave
Figure
Start Bit.
Data Bit.
Acknowledge Waveform.
5-2) indicates the beginning of
1st Bit
1st Bit
5-3).
9
A
2nd Bit
2nd Bit
If the Slave Address is not valid, the Slave Device will
issue a Not A (A). The A bit will have the SDA signal
high.
If an error condition occurs (such as an A instead of A)
then a START bit must be issued to reset the command
state machine.
TABLE 5-1:
5.2.4
The Repeated Start bit (see
the current
communicating with the current Slave Device without
releasing the I
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 5-5:
Waveform.
SDA
General Call
Slave Address
valid
Slave Address
not valid
Bus Collision
SCL
Note 1: A bus collision during the Repeated Start
Event
REPEATED START BIT
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
condition occurs if:
Master
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
2
C bus. The Repeated Start condition is
Acknowledge
Bit Response
MCP40D17/18/19 A / A
RESPONSES
N.A.
Device
Repeat Start Condition
A
A
A
© 2009 Microchip Technology Inc.
wishes
Figure
I
or a “Don’t Care” if
the collision occurs
on the Masters
“Start bit”.
Sr = Repeated Start
2
C Module Resets,
Comment
5-5) indicates
to
1st Bit
continue