MCP2030 Microchip Technology Inc., MCP2030 Datasheet - Page 50

• Manufacturer Part Number: MCP2030
• Description: Three-channel Analog Front-end Device
• Manufacturer: Microchip Technology Inc.

MCP2030
FIGURE 5-12:
5.31.2.1
This command results in activating (turning on) the
modulation transistors of all enabled channels; channels
enabled in Configuration Register 0 (Register 5-1).
5.31.2.2
This command results in deactivating (turning off) the
modulation transistors of all channels.
5.31.2.3
This command places the device in Sleep mode –
minimizing current draw by disabling all but the
essential circuitry. Any other command wakes the
device from Sleep (e.g., Clamp Off command).
5.31.2.4
The device issues a Soft Reset when it receives an
external Soft Reset command. The external Soft Reset
command is typically used to end a SPI communication
sequence or to initialize the device for the next signal
detection sequence, etc. See Section 5.20 “Soft
Reset” for more details on Soft Reset.
If a Soft Reset command is sent during a “Clamp-on”
condition, the device still keeps the “Clamp-on” condi-
tion after the Soft Reset execution. The Soft Reset is
executed in Active mode only, not in Standby mode.
The SPI Soft Reset command is ignored if the device is
not in Active mode.
DS21981A-page 50
SCLK
SDIO
CS
Clamp On Command
Clamp Off Command
Sleep Command
Soft Reset Command
Detailed SPI Timing (AFE).
MSb
1
Command
2
3
4
Address
5
6
7
8
5.31.2.5
This command results in preserving the AGC level
during each AGC initialization time and apply the value
to the data slicing circuit for the following data stream.
The preserved AGC value is reset by a Soft Reset, and
a new AGC value is acquired and preserved when it
starts a new AGC initialization time. This feature is
disabled by an AGC Preserve Off command (see
Section 5.19 “AGC Preserve”).
5.31.2.6
This command disables the AGC preserve feature and
returns to the normal AGC tracking mode, fast tracking
during AGC settling time and slow tracking after that
(see Section 5.19 “AGC Preserve”).
5.31.3
The device includes 8 Configuration registers, includ-
ing a Column Parity register and STATUS register. All
registers are readable and writable via SPI, except the
STATUS register, which is read-only. Bit 0 of each
register is a row parity bit (except for STATUS Register
7) that makes the register contents an odd number.
9
10
Data Byte
11
READ/WRITE COMMANDS FOR
CONFIGURATION REGISTERS
AGC Preserve On Command
AGC Preserve Off Command
12
13
© 2005 Microchip Technology Inc.
14
15
Parity Bit
Row
LSb
16