MCP2030 Microchip Technology Inc., MCP2030 Datasheet - Page 51

• Manufacturer Part Number: MCP2030
• Description: Three-channel Analog Front-end Device
• Manufacturer: Microchip Technology Inc.

TABLE 5-6:
REGISTER 5-1:
© 2005 Microchip Technology Inc.
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5 AUTOCHSEL AGCSIG
Column Parity Register 6
STATUS Register 7
Register Name
bit 8-7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
-n = Value at POR
CONFIGURATION REGISTERS SUMMARY
CONFIGURATION REGISTER 0 (ADDRESS: 0000)
OEH<1:0>: Output Enable Filter High Time (
00 = Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA)
01 = 1 ms
10 = 2 ms
11 = 4 ms
OEL<1:0>: Output Enable Filter Low Time (T
00 = 1 ms
01 = 1 ms
10 = 2 ms
11 = 4 ms
ALRTIND: ALERT bit, output triggered by:
1 = Parity error and/or expired Alarm timer (receiving noise, see Section 5.14.3 “Alarm Timer”)
0 = Parity error
LCZEN: LCZ Enable bit
1 = Disabled
0 = Enabled
LCYEN: LCY Enable bit
1 = Disabled
0 = Enabled
LCXEN: LCX Enable bit
1 = Disabled
0 = Enabled
R0PAR: Register 0 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of
set bits
bit 8
R/W-0
OEH1
RSSIFET
Bit 8
Unimplemented
Active Channel Indicators
DATOUT
Channel X Sensitivity Control
OEH
R/W-0
OEH0
W = Writable bit
‘1’ = Bit is set
CLKDIV
Bit 7
R/W-0
OEL1
MODMIN MODMIN
Bit 6
OEL
R/W-0
OEL0
Column Parity Bits
AGCACT
Bit 5
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
T
OEL
OEH
Channel X Tuning Capacitor
Channel Y Tuning Capacitor
Channel Z Tuning Capacitor
ALRTIND
) bit
R/W-0
) bit
ALRTIND
Wake-up Channel Indicators
Bit 4
Channel Y Sensitivity Control
Channel Z Sensitivity Control
LCZEN
R/W-0
LCZEN
Bit 3
LCYEN
R/W-0
LCYEN
Bit 2
MCP2030
x = Bit is unknown
LCXEN
R/W-0
ALARM
LCXEN
DS21981A-page 51
Bit 1
R0PAR
R0PAR
R1PAR
R2PAR
R3PAR
R4PAR
R5PAR
R6PAR
R/W-0
Bit 0
PEI
bit 0