MCP1754 Microchip Technology Inc., MCP1754 Datasheet - Page 18

• Manufacturer Part Number: MCP1754
• Description: 150 Ma, 16v, High Performance Ldo
• Manufacturer: Microchip Technology Inc.

MCP1754/MCP1754S
4.4
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent or higher value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5
The open drain PWRGD output is used to indicate
when the output voltage of the LDO is within 94%
(typical
Characteristics”
specifications) of its nominal regulation value.
As the output voltage of the LDO rises, the open drain
PWRGD output will actively be held low until the output
voltage has exceeded the power good threshold plus
the hysteresis value. Once this threshold has been
exceeded, the power good time delay is started (shown
as T
power good time delay is fixed at 100 µs (typical). After
the time delay period, the PWRGD open drain output
becomes inactive and may be pulled high by an
external pullup resistor, indicating that the output
voltage is stable and within regulation limits. The power
good output is typically pulled up to V
the signal up to V
shutdown mode.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 200 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
DS22276A-page 18
PG
applications
in the Electrical Characteristics table). The
Input Capacitor
Power Good Output (PWRGD)
value,
see
for
that
OUT
minimum
have
Section 1.0
Figure 4-2
conserves power during
output
IN
and
or V
for power good
OUT
step
“Electrical
maximum
. Pulling
load
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA minimum (V
FIGURE 4-2:
FIGURE 4-3:
Shutdown.
4.6
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a fixed
voltage level. The minimum value of this shutdown
threshold required to turn the output ON is 2.4V. The
maximum value required to turn the output OFF is 0.8V.
V
VPWRGD_TH
PWRGD
V
IN
SHDN
OUT
VOUT
PWRGD
4-3.
Shutdown Input (SHDN)
T
DELAY_SHDN
TPG
PWRGD
Power Good Timing.
Power Good Timing from
VOH
© 2011 Microchip Technology Inc.
< 0.4V maximum).
T
PG
TVDET_PWRGD
VOL