IDT72V805L15PFI IDT, Integrated Device Technology Inc, IDT72V805L15PFI Datasheet - Page 24

• Manufacturer Part Number: IDT72V805L15PFI
• Description: IC FIFO SYNC 256X18 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V805L15PFI

• Function: Asynchronous, Synchronous
• Memory Size: 4.6K (256 x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V805L15PFI

DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using one IDT72V805/72V815/72V825/72V835/72V845s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72V805/72V815/72V825/72V835/72V845
devices.
WRITE ENABLE
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
WRITE CLOCK
These devices can easily be adapted to applications requiring more than
1. The first device must be designated by grounding the First Load (FL)
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the
In FWFT mode, the FIFOs can be connected in series (the data outputs
control input.
DATA IN
RESET
LOAD
PAF
FF
Figure 30. Block Diagram of 8,192 x 18 Synchronous FIFO Memory with Programmable Flags
FIRST LOAD (FL)
IDT72V845
Vcc
Used in Depth Expansion Configuration
WCLKA
WENA
RSA
LDA
DAn
FLA
FFA/IRA
PAFA
WENB
WCLKB
RSB
DBn
FFA/IRA EFA/ORA
PAFB
LDB
WXOA
WXOB
WXIA
WXIB
4,096 x 18
4,096 x 18
FIFO A
FIFO B
EFA/ORA
RCLKA
RCLKB
RXOA
RXIA
RXOB
RXIB
RENA
RENB
PAEA
PAEB
QAn
OEA
OEB
QBn
24
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (“ripple down”) until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
5. All Load (LD) pins are tied together.
6. The Half-Full flag (HF) is not available in this Depth Expansion
7. EF, FF, PAE, and PAF are created with composite flags by ORing
8. In Daisy Chain mode, the flag outputs are single register-buffered and
Care should be taken to select FWFT mode during Master Reset for all
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
the partial flags are in asynchronous timing mode.
Write Expansion In (WXI) pin of the next device. See Figure 30.
Read Expansion In (RXI) pin of the next device. See Figure 30
Configuration.
COMMERCIAL AND INDUSTRIAL
PAE
TEMPERATURE RANGES
EF
FEBRUARY 11, 2009
READ CLOCK
READ ENABLE
DATA OUT
OUTPUT ENABLE
4295 drw 30