IDT72V851L15PF IDT, Integrated Device Technology Inc, IDT72V851L15PF Datasheet - Page 14

• Manufacturer Part Number: IDT72V851L15PF
• Description: IC FIFO SYNC 4096X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V851L15PF

• Function: Asynchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 8Kx9x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V851L15PF

OPERATING CONFIGURATIONS
Device Configuration, the Read Enable 2 RENA2 (RENB2) control input can
creased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the end-
point status flags EFA and EFB, also FFA and FFB). The partial status flags PAEA,
PAFB, PAEA and PAFB can be detected from any one device. Figure 15
demonstrates an 18-bit word width using the two FIFOs contained in one
IDT72V801/72V811/72V821/72V831/72V841/72V851. Any word width can
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
WIDTH EXPANSION CONFIGURATION — Word width may be in-
WRITE ENABLE
DATA IN
WRITE CLOCK
WRITE ENABLE/LOAD
FULL FLAG
Figure 15. Block diagram of the two FIFOs contained in one IDT72V801/72V811/72V821/72V831/72V841/72V851
18
Figure 14. Block Diagram of One of the IDT72V801/72V811/72V821/72V831/72V841/72V851's
WENA2/LDA (WENB2/LDB)
9
DA
0
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2/LDA
- DA
FFB
DA0 - DA8
WCLKA
WENA1
FFA
PAFA (PAFB)
8
(DB
FFA (FFB)
0
configured for an 18-bit width-expansion
two FIFOs configured as a single device
- DB
RSA
ARRAY
1,024x9
2,048x9
4,096x9
8,192x9
8
256x9
512x9
RAM
)
A
RENA2
9
DB0 - DB8
RCLKA
2WENB2/LDB
RENA1
OEA1
72V801
72V811
72V821
72V831
72V841
72V851
FIFO
14
A (B)
WCLKB
WENB1
IDT
QA0 - QA8
be grounded (see Figure 14). In this configuration, the Write Enable 2/Load
WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
be attained by adding additional IDT72V801/72V811/72V821/72V831/
72V841/72V851s.
Enable 2 (RENA2 and RENB2) control inputs can be grounded (see Figure
15). In this configuration, the Write Enable 2/Load (WENA2/LDA, WENB2/LDB)
pins are set LOW at Reset so that the pin operates as a control to load and read
the programmable flag offsets.
RSA (RSB)
RENA2 (RENB2)
When these devices are in a Width Expansion Configuration, the Read
RSB
9
1,024x9
2,048x9
4,096x9
8,192x9
ARRAY
256x9
512x9
TM
RAM
B
RENB2
RCLKA (RCLKB)
RENA1 (RENB1)
OEA (OEB)
QA
EFA (EFB)
PAEA (PAEB)
0
- QA
QB0 - QB8
RCLKB
RENB1
OEB
8
EFA
EFB
(QB
0
- QB
8
)
COMMERCIAL AND INDUSTRIAL
9
TEMPERATURE RANGES
OUTPUT ENABLE
OCTOBER 22, 2008
18
READ ENABLE
READ CLOCK
EMPTY FLAG
DATA OUT
4093 drw 16
4093 drw 17
RESET