AD8330 Analog Devices, AD8330 Datasheet - Page 20

• Manufacturer Part Number: AD8330
• Description: Low Cost DC-150MHz Variable Gain Amplifier
• Manufacturer: Analog Devices

AD8330
Using Single-Sided Sources and Loads
Where the source provides a single-sided output, either INHI or
INLO may be used for the input, with of course a polarity change
when using INLO. The unused pin must be connected either
through a capacitor to ground, or a dc bias point that corresponds
closely to the dc level on the active signal pin. The input CMRR
over the full frequency range is illustrated in Figure 16. In some
cases, an additional element such as a SAW filter (having a single-
sided-balanced configuration) or a flux-coupled transformer may
be interposed. Where this element must be terminated in the
correct impedance, other than 1 k , it will be necessary to add
either shunt or series resistors at this interface.
Figure 17. AC Gain and Phase for Various Loading Conditions
When driving a single-sided load, either OPHI or OPLO may be
used. These outputs are very symmetric, so the only effect of
this choice is to select the desired polarity. However, when the
frequency range of interest extends to the upper limits of the
AD8330, a dummy resistor of the same value should be attached
to the unused output. Figure 17 illustrates the ac gain and phase
response for various loads and V
unloaded (C
(20 dB) using just the single-sided output. Adding a 75
just from OPHI to an ac ground results in Line 2. The gain is
now a factor of 1.5 or 3.54 dB lower, but artifacts of the output
common-mode control loop now appear in both the magnitude
and phase response.
Figure 16. Input CMRR vs. Frequency for Various
Values of V
–100
–200
–300
–400
–500
–600
–10
–20
–30
–10
30
20
10
90
80
70
60
50
40
30
20
10
0
0
0
50k
1M
L
V
100k
= 12 pF) case for reference; the gain is 6 dB lower
DBS
V
DBS
= 0V
DBS
= 1.5V
V
DBS
10M
= .75V
FREQUENCY – Hz
FREQUENCY – Hz
1M
DBS
= 0.75 V. Line 1 shows the
OFST: ENABLED
DISABLED
10M
100M
LINE 4
LINE 4
LINE 1
LINE 2
LINE 2
LINE 1
LINE 3
LINE 3
500M
100M
load
–20–
Adding a dummy 75
further 2.5 dB lower, at about 14 dB. The CM artifacts are no
longer present but there is now a small amount of peaking. If
objectionable, this may be eliminated by raising both of the
capacitors on the output pins to 25 pF, as shown in Line 4.
The gain reduction incurred both by using only one output and
by the additional effect of loading can be overcome by taking
advantage of the V
circumstances. Thus, to restore the basic gain in the first case
(Line 1), a 1 V source should be applied to this pin; to restore
the gain in the second case, this voltage should be raised by a
factor of 1.5, to 1.5 V. In cases 3 and 4, a further factor of
be raised to 2 V. With the restoration of gain, the peak output
swing at the load is likewise restored to 2 V.
Pulse Operation
When using the AD8330 in applications where its transient response
is of greater interest and the outputs are conveyed to their load via
coaxial cables, the added capacitances may be slightly different in
value, and may be placed either at the sending or load end of the
cables, or divided between these nodes. Figure 18 shows an illustra-
tive example in which dual 1 meter 75
dc-blocking capacitors and independently terminated at ground level.
Because of the considerable variation between applications, only
general recommendations can be made with regard to minimizing
pulse overshoot and droop. The former can be optimized by adding
small load capacitances, if necessary; the latter require the use
of sufficiently large capacitors C1.
1.33 is needed to make up the 2.5 dB loss, that is, V
VPSI
INHI
INLO
MODE
Figure 18. Driving Dual Cables with Grounded Loads
ENBL
VDBS
BIAS AND
V-REF
VGA CORE
GAIN INTERFACE
OFST
CMGN
MAG
CM MODE AND
OFFSET CONTROL
feature, provided primarily for just such
to OPLO results in Line 3: the gain is a
VPOS
COMM
OUTPUT
STAGES
OUTPUT
CONTROL
CNTR
VMAG
NC
VPSO
OPHI
OPLO
CMOP
cables are driven through
CD2
CD3
C1
C1
RD2
CL1
CL2
MAG
V
REV. A
S
2.7V–6V
should
RL1
RL2