AD8330 Analog Devices, AD8330 Datasheet - Page 23

• Manufacturer Part Number: AD8330
• Description: Low Cost DC-150MHz Variable Gain Amplifier
• Manufacturer: Analog Devices

Figure 20 shows the connections. A 3.3 V supply is used for
both parts. The ADC requires that its input pins be positioned
at one third of the supply, or 1.1 V. Since the default output
level of the VGA is one half the supply or 1.65 V, a small correc-
tion is introduced by the 8 k resistor from CNTR to ground.
The ADC specifications require that the common-mode input
be within 0.2 V of the nominal 1.1 V; variations of up to 20%
in the AD8330’s on-chip resistors will change this voltage by
only 70 mV. With the connections shown, the AD9214 is able
to receive an input of 2 V p-p; the peak output of the AD8330
can be reduced if desired by adding a resistor from VMAG to
ground. An overrange condition is signaled by a HI state on pin
OR of the AD9214. DFS/GAIN is unconnected in this example;
this produces an offset-binary output. To provide a twos comple-
ment output, it should be connected to the REF pin.
For ADCs running at sampling rates substantially below the
bandwidth of the AD8330, an intervening noise filter is recom-
mended to limit the noise bandwidth. A one-pole filter can
easily be created with a single differential capacitor between
OPHI and OPLO outputs. For a corner frequency of fc, the
capacitor should have a value of
For example a 10 MHz corner requires about 100 pF.
Simple AGC Amplifier
Figure 21 illustrates the use of the inverted gain mode and the
offset gain range (0.2 V < V
AGC loop. Q1 is used as a detector: when OPHI is sufficiently
higher than CNTR, due to the signal swing it conducts and
charges C1; this raises V
that MODE is grounded (see Figure 5). The minimum voltage
needed across R1 to set up the full gain is now 0.2 V, since
CMGN is dc open-circuited (this does not alter V
maximum is 1.7 V.
REV. A
C
FILT
1 942
/
INPUT,
f
C
2V MAX
10
0.1 F
NC
GAIN BIAS,
V
DBS
DBS
, 0V–1.5V
DBS
VPSI
INHI
INLO
MODE
and rapidly lowers the gain. Note
ENBL
VDBS
< 1.7 V) in supporting a low cost
Figure 20. Driving an Analog-to-Digital Converter (Preliminary)
BIAS AND
V-REF
VGA CORE
GAIN INTERFACE
OFST
CMGN
CHPF
CM MODE AND
OFFSET CONTROL
VPOS
MAG
COMM
OUTPUT
STAGES
OUTPUT
CONTROL
ANALOG GROUND
), while the
0.1 F
CNTR
VMAG
NC
VPSO
OPHI
OPLO
CMOP
(26)
8k
–23–
0.1 F
When the loop is settled, the average current in Q1 is V
which varies from 2 A at maximum gain (V
rent causes an increase of ~0.25 dB over the full gain range in
the differential output of nominally 0.75 dBV at midrange (3.08
V p-p), corresponding to a 200:1 compression ratio. This is
plotted in Figure 22 for a representative 100 kHz input.
5mV TO 1V rms
A at minimum gain (V
0.1 F
INPUT,
PWRDN
DFS/GAIN
REFSENSE
REF
A
A
IN
IN
10
0.1 F
Figure 21. Simple AGC Amplifier (Preliminary)
AV
AGND
DD
100k
VPSI
INHI
INLO
MODE
ENBL
VDBS
R1
3.3
AD9217BRS-80
BIAS AND
V-REF
VGA CORE
GAIN INTERFACE
RANGE
OVER-
CLOCK
OR
CLK
OFST
CMGN
DBS
0.1 F
33nF
= 1.7 V). This change in Q1’s cur-
CM MODE AND
OFFSET CONTROL
DrV
DGND
VPOS
GROUND
3.3
DIGITAL
COMM
OUTPUT
STAGES
DD
OUTPUT
CONTROL
0.1 F
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V
S
, 3.3V
CNTR
VMAG
NC
VPSO
OPHI
OPLO
CMOP
DBS
AD8330
= 0.2 V) to 17
TEXT
4.7
SEE
0.1 F
Q2
C1
0.1 F
V
DBS
S
, 2.7V–6V
OUTPUT,
~1V rms
Q1
/R1,
0.1 F