IDT72V263L10PFI IDT, Integrated Device Technology Inc, IDT72V263L10PFI Datasheet - Page 42

• Manufacturer Part Number: IDT72V263L10PFI
• Description: IC FIFO 8192X18 10NS 80QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L10PFI

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 6.5ns
• Word Size: 18/9Bit
• Organization: 8Kx18/16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 30@9BIT/35@18BITmA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V263L10PFI

TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap
controller and modified pad cells to implement the JTAG facility.
program files for these devices.
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
The Tap interface is a general-purpose port that provides access to the
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
UpdateDR
Figure 32. Boundary Scan Architecture
Instruction Register
Control Signals
42
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TM
The Standard JTAG interface consists of four basic elements:
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The Tap controller is a synchronous finite state machine that responds to
NARROW BUS FIFO
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Instruction Decode
Mux
4666 drw35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009