IDT72V263L6PFG IDT, Integrated Device Technology Inc, IDT72V263L6PFG Datasheet - Page 12

• Manufacturer Part Number: IDT72V263L6PFG
• Description: IC FIFO 8192X18 6NS 80QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V263L6PFG

• Function: Asynchronous, Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 166MHz
• Access Time: 4ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V263L6PFG

FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
72V293 support two different timing modes of operation: IDT Standard mode
or First Word Fall Through (FWFT) mode. The selection of which mode will
operate is determined during Master Reset, by the state of the FWFT/SI input.
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
on which timing mode is in effect.
IDT STANDARD MODE
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 257th word for the IDT72V223, 513rd word for
IDT72V233, 1,025th word for the IDT72V243, 2,049th word for the IDT72V253,
4,097th word for the IDT72V263, 8,193th word for IDT72V273, 16,385th word
for the IDT72V283 and 32,769th word for the IDT72V293. If both x9 Input and
x9 Output bus Widths are selected, (D/2 + 1) = the 513rd word for the
IDT72V223, 1,025th word for IDT72V233, 2,049th word for the IDT72V243,
4,097th word for the IDT72V253, 8,193rd word for the IDT72V263, 16,385th
word for IDT72V273, 32,769th word for the IDT72V283 and 65,537th word
for the IDT72V293. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or
x18 Output bus Width is selected, (D-m) = (512-m) writes for the IDT72V223,
(1,024-m) writes for the IDT72V233, (2,048-m) writes for the IDT72V243 and
(4,096-m) writes for the IDT72V253, (8,192-m) writes for the IDT72V263,
(16,384-m) writes for the IDT72V273, (32,768-m) writes for the IDT72V283
and (65,536-m) writes for the IDT72V293. If both x9 Input and x9 Output bus
Widths are selected, (D-m) = (1,024-m) writes for the IDT72V223, (2,048-m)
writes for the IDT72V233, (4,096-m) writes for the IDT72V243, (8,192-m)
writes for the IDT72V253, (16,384-m) writes for the IDT72V263, (32,768-m)
writes for the IDT72V273, (65,536-m) writes for the IDT72V283 and (131,072-m)
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
Various signals, both input and output signals operate differently depending
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
If one continued to write data into the FIFO, and we assumed no read
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
n)
. It also uses Input Ready (IR) to indicate
n
after three RCLK rising
12
writes for the IDT72V293. The offset “m” is the full offset value. The default setting
for these values are stated in the footnote of Table 2. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 512 writes
for the IDT72V223, 1,024 writes for the IDT72V233, 2,048 writes for the
IDT72V243, 4,096 writes for the IDT72V253, 8,192 writes for the IDT72V263,
16,384 writes for the IDT72V273, 32,768 writes for the IDT72V283 and 65,536
writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected,
D = 1024 writes for the IDT72V223, 2,048 writes for the IDT72V233, 4,096
writes for the IDT72V243, 8,192 writes for the IDT72V253, 16,384 writes for
the IDT72V263, 32,768 writes for the IDT72V273, 65,536 writes for the
IDT72V283 and 131,072 writes for the IDT72V293, respectively.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
register-buffered outputs.
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
manner outlined in Table 4. To write data into the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
operations were taking place, the HF would toggle to LOW once the (D/2 + 2)
words were written into the FIFO. If x18 Input or x18 Output bus Width is selected,
(D/2 + 2) = the 258th word for the IDT72V223, 514th word for IDT72V233,
1,026th word for the IDT72V243, 2,050th word for the IDT72V253, 4,098th
word for the IDT72V263, 8,194th word for IDT72V273, 16,386th word for the
IDT72V283 and 32,770th word for the IDT72V293. If both x9 Input and x9
Output bus Widths are selected, (D/2 + 2) = the 514th word for the IDT72V223,
1,026th word for IDT72V233, 2,050th word for the IDT72V243, 4,098th word
for the IDT72V253, 8,194th word for the IDT72V263, 16,386th word for
IDT72V273, 32,770th word for the IDT72V283 and 65,538th word for the
IDT72V293. Continuing to write data into the FIFO will cause the PAF to go LOW.
Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the
FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (513-m) writes
for the IDT72V223, (1,025-m) writes for the IDT72V233, (2,049-m) writes for
the IDT72V243, (4,097-m) writes for the IDT72V253, (8,193-m) writes for the
IDT72V263, (16,385-m) writes for the IDT72V273, (32,769-m) writes for the
IDT72V283 and (65,537-m) writes for the IDT72V293. If both x9 Input and x9
Output bus Widths are selected, (D-m) = (1,025-m) writes for the IDT72V223,
(2,049-m) writes for the IDT72V233, (4,097-m) writes for the IDT72V243,
(8,193-m) writes for the IDT72V253, (16,385-m) writes for the IDT72V263,
TM
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
If the FIFO is full, the first read operation will cause FF to go HIGH.
When configured in IDT Standard mode, the EF and FF outputs are double
Relevant timing diagrams for IDT Standard mode can be found in Figure
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
If one continued to write data into the FIFO, and we assumed no read
NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009