SN74LS114D Motorola, SN74LS114D Datasheet

SN74LS114D

Manufacturer Part Number

SN74LS114D

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacturer

Motorola

Datasheet

1.SN74LS114D.pdf (4 pages)

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DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

individual J, K, and set inputs. These monolithic dual flip-flops are designed

so that when the clock goes HIGH, the inputs are enabled and data will be

accepted. The logic level of the J and K inputs may be allowed to change when

the clock pulse is HIGH and the bistable will perform according to the truth

table as long as minimum set-up times are observed. Input data is transferred

to the outputs on the negative-going edge of the clock pulse.

* Both outputs will be HIGH while both S D and C D are LOW, but the output states

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output)

l, h (q) =

FLIP FLOP

Set

Reset (Clear)

*Undetermined

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

are unpredictable if S D and C D go HIGH simultaneously.

The SN54/ 74LS114A offers common clock and common clear inputs and

OTHER

OPERATING MODE

CLEAR (C D )

one set-up time prior to the HIGH to LOW clock transition.

5(9)

3(11)

MODE SELECT — TRUTH TABLE

LOGIC DIAGRAM (Each Flip-Flop)

S D

C D

INPUTS

CLOCK (CP)

FAST AND LS TTL DATA

OUTPUTS

5-193

6(8)

4(10)

2(12)

SET (S D )

EDGE-TRIGGERED FLIP-FLOP

SN54/74LS114A

ORDERING INFORMATION

LOW POWER SCHOTTKY

SN54LSXXXJ

SN74LSXXXN Plastic

SN74LSXXXD SOIC

DUAL JK NEGATIVE

K C

LOGIC SYMBOL

S D

V CC = PIN 14

GND = PIN 7

Ceramic

CASE 751A-02

CASE 632-08

CASE 646-06

CERAMIC

N SUFFIX

D SUFFIX

J SUFFIX

PLASTIC

SOIC

C D

S D

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