SN74LS256N

Manufacturer Part NumberSN74LS256N
DescriptionDUAL 4-BIT ADDRESSABLE LATCH
ManufacturerMotorola
SN74LS256N datasheet
 


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DUAL 4-BIT
ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control
inputs; these include two Address inputs (A 0 , A 1 ), an active LOW Enable input
(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and
four outputs (Q 0 – Q 3 ).
When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs
(Q 0 – Q 3 ) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and
E are both LOW. When CL is HIGH and E is LOW, the selected output
(Q 0 – Q 3 ), determined by the Address inputs, follows D. When the E goes
HIGH, the contents of the latch are stored. When operating in the addressable
latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address
(A 0 , A 1 ) could impose a transient wrong address. Therefore, this should be
done only while in the memory mode (E= CL = HIGH).
Serial-to-Parallel Capability
Output From Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Active Low Common Clear
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
V CC
CL
E
D b
Q 3b
Q 2b
Q 1b
16
15
14
13
12
11
10
1
2
3
4
5
6
A 0
A 1
D a
Q 0a
Q 1a
Q 2a
Q 3a
PIN NAMES
A 0 , A 1
Address Inputs
D a , D b
Data Inputs
E
Enable Input (Active LOW)
CL
Clear Input (Active LOW)
Q 0a – Q 3a ,
Q 0b – Q 3b
Parallel Latch Outputs (Note b)
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
Q 0b
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
7
8
GND
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
10 U.L.
5 (2.5) U.L.
FAST AND LS TTL DATA
5-421
SN54/74LS256
DUAL 4-BIT
ADDRESSABLE LATCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
16
CASE 751B-03
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
LOGIC SYMBOL
3
2 1 15
14 13
D a
E
E
D b
A 0
A 0
A 1
A 1
CL
CL
Q 0a Q 1a Q 2a Q 3a
Q 0b Q 1b Q 2b Q 3b
4
5
6
7
9
10
11
12
V CC = PIN 16
GND = PIN 8

SN74LS256N Summary of contents

  • Page 1

    DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs ( active LOW Enable input (E) and an active LOW Clear input (CL). ...

  • Page 2

    LOGIC DIAGRAM PIN 16 GND = PIN 8 = PIN NUMBERS ...

  • Page 3

    GUARANTEED OPERATING RANGES Symbol Parameter V CC Supply Voltage T A Operating Ambient Temperature Range I OH Output Current — High I OL Output Current — Low DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Symbol Symbol Parameter Parameter V IH Input ...

  • Page 4

    AC SET-UP REQUIREMENTS ( Symbol Symbol Parameter Parameter t s Data Setup Time t s Address Setup Time t h Data Hold Time t h Address Hold Time t W Enable Pulse Width ...

  • Page 5

    G - 0.25 (0.010 - SEATING -T- PLANE 0.25 (0.010) ...

  • Page 6

    ... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...