LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 68

• Manufacturer Part Number: LM3S1607
• Description: Lm3s1607 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
6.2
6.3
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Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1.
2.
3.
4.
5.
Register Map
Table 6-1 on page 69 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note:
Note:
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 147.
Preliminary
June 02, 2008