LM3S6610 Luminary Micro, Inc, LM3S6610 Datasheet - Page 418

• Manufacturer Part Number: LM3S6610
• Description: Lm3s6610 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Ethernet Controller
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
418
Bit/Field
9:6
RPTR
15
14
13
12
11
10
R/W
15
0
INPOL
R/W
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the PHY.
14
0
reserved
reserved
reserved
RO
13
TXHIM
INPOL
0
Name
RPTR
SQEI
NL10
TXHIM
R/W
12
0
SQEI
R/W
11
0
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
NL10
R/W
10
0
Reset
0x05
RO
9
0
0
0
0
0
0
0
Preliminary
RO
8
1
Description
Repeater Mode
When set, enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity. If the PHY is configured to 10Base-T mode, the SQE
test function is disabled.
Interrupt Polarity
Important:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit High Impedance Mode
When set, enables the transmitter High Impedance mode. In this mode,
the TXOP and TXON transmitter pins are put into a high impedance state.
The RXIP and RXIN pins remain fully functional.
SQE Inhibit Testing
When set, prohibits 10Base-T SQE testing.
When 0, the SQE testing is performed by generating a Collision pulse
following the completion of the transmission of a frame.
Natural Loopback Mode
When set, enables the 10Base-T Natural Loopback mode. This causes
the transmission data received by the PHY to be looped back onto the
receive data path when 10Base-T mode is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Value
reserved
1
0
RO
Description
Sets the polarity of the PHY interrupt to be active High.
Sets the polarity of the PHY interrupt to active Low.
7
0
Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
RO
6
1
APOL
R/W
5
0
RVSPOL
R/W
4
0
RO
3
0
reserved
RO
2
0
July 25, 2008
PCSBP
R/W
1
0
RXCC
R/W
0
0