LM3S6610 Luminary Micro, Inc, LM3S6610 Datasheet - Page 87

• Manufacturer Part Number: LM3S6610
• Description: Lm3s6610 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
July 25, 2008
Bit/Field
31:29
28:23
22:7
6:4
3:0
RO
RO
31
15
0
0
reserved
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
RO
RO
30
14
0
0
DSDIVORIDE
DSOSCSRC
reserved
reserved
reserved
RO
RO
29
13
0
0
Name
R/W
RO
28
12
0
0
reserved
R/W
RO
27
11
0
0
Type
R/W
R/W
RO
RO
RO
R/W
RO
DSDIVORIDE
26
10
1
0
Reset
0x0F
R/W
0x0
0x0
0x0
0x0
RO
25
1
9
0
Preliminary
R/W
RO
24
1
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Source
Specifies the clock source during Deep-Sleep mode.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Value
0x0
0x1
0x3
0x7
R/W
RO
23
Description
NOORIDE
No override to the oscillator clock source is done.
IOSC
Use internal 12 MHz oscillator as source.
30kHz
Use 30 kHz internal oscillator.
32kHz
Use 32 kHz external oscillator.
1
7
0
R/W
RO
22
0
6
0
DSOSCSRC
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
reserved
LM3S6610 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
RO
RO
16
0
0
0
87