LM3S6918 Luminary Micro, Inc, LM3S6918 Datasheet - Page 78

• Manufacturer Part Number: LM3S6918
• Description: Lm3s6918 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
78
Bit/Field
26:23
21:14
22
13
12
USESYSDIV
reserved
reserved
PWRDN
SYSDIV
Name
Type
R/W
R/W
R/W
RO
RO
Reset
0xF
0
0
1
1
Preliminary
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
When reading the Run-Mode Clock Configuration (RCC) register (see
page 77), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Divisor (BYPASS=1)
reserved
/2
/3
/4
/5
/6
/7
/8
/9
/10
/11
/12
/13
/14
/15
/16
Frequency (BYPASS=0)
reserved
reserved
reserved
50 MHz
40 MHz
33.33 MHz
28.57 MHz
25 MHz
22.22 MHz
20 MHz
18.18 MHz
16.67 MHz
15.38 MHz
14.29 MHz
13.33 MHz
12.5 MHz (default)
July 26, 2008