LM3S6938 Luminary Micro, Inc, LM3S6938 Datasheet - Page 432

• Manufacturer Part Number: LM3S6938
• Description: Lm3s6938 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Ethernet Controller
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
432
Bit/Field
31:6
5:0
RO
RO
31
15
0
0
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until
the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature.
Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When
THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in
the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight
writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to
be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission
starts when:
Number of Bytes >= 4 (THRESH x 8 + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is sent out on the physical medium. Because under-run checking is not performed, it is possible
that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate
values to be written to the physical medium rather than the end of the frame. Therefore, sufficient
bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register
must be set with an explicit write. This initiates the transmission of the frame even though the
threshold limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs.
RO
RO
30
14
0
0
THRESH
reserved
RO
RO
29
13
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
reserved
Type
R/W
RO
RO
RO
26
10
0
0
Reset
0x3F
0x0
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds this value, transmission of the packet
begins.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
R/W
RO
19
0
3
1
THRESH
R/W
RO
18
0
2
1
July 25, 2008
R/W
RO
17
0
1
1
R/W
RO
16
0
0
1