LM3S6938 Luminary Micro, Inc, LM3S6938 Datasheet - Page 44

• Manufacturer Part Number: LM3S6938
• Description: Lm3s6938 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Interrupts
4
44
Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 44 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 32 interrupts (listed in Table 4-2 on page 45).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
Important:
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type
-
Reset
Non-Maskable
Interrupt (NMI)
Hard Fault
Memory Management
It may take several processor cycles after a write to clear an interrupt source in order
for NVIC to see the interrupt source de-assert. This means if the interrupt clear is done
as the last action in an interrupt handler, it is possible for the interrupt handler to complete
while NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This can be avoided by either clearing the interrupt source at the
beginning of the interrupt handler or by performing a read or write after the write to clear
the interrupt source (and flush the write buffer).
Vector
Number
0
1
2
3
4
Priority
-3 (highest)
settable
-2
-1
-
a
Preliminary
Description
Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
July 25, 2008