LM3S6952 Luminary Micro, Inc, LM3S6952 Datasheet - Page 419

• Manufacturer Part Number: LM3S6952
• Description: Lm3s6952 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

16.2.1
16.2.2
16.2.2.1 Clock Selection
16.2.2.2 Auto-Negotiation
16.2.2.3 Polarity Correction
16.2.2.4 MDI/MDI-X Configuration
July 25, 2008
Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer auto-negotiates the link parameters by default.
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider
used for scaling down the system clock. See page 438 for more details about the use of this register.
PHY Configuration/Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this
mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY
pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this
mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset.
Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the
MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual
speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the
ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing
a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart.
The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation
functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is
automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted
the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the
signal polarity.
The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. This eliminates the need for cross-over cables when connecting to another device,
such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 460 for
additional details about these settings.
Preliminary
LM3S6952 Microcontroller
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