LM3S8971 Luminary Micro, Inc, LM3S8971 Datasheet - Page 111

• Manufacturer Part Number: LM3S8971
• Description: Lm3s8971 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
July 26, 2008
Bit/Field
31:25
23:20
24
19
18
RO
RO
31
15
0
0
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
RO
RO
30
14
0
0
reserved
reserved
RO
RO
TIMER3
TIMER2
COMP0
29
13
0
0
Name
reserved
reserved
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
RO
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
COMP0
QEI0
R/W
R/W
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
RO
RO
23
0
7
0
reserved
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
SSI0
R/W
RO
20
0
4
0
TIMER3
LM3S8971 Microcontroller
R/W
RO
19
0
3
0
reserved
TIMER2
R/W
RO
18
0
2
0
TIMER1
R/W
RO
17
0
1
0
TIMER0
UART0
R/W
R/W
16
0
0
0
111