LM3S2651 Luminary Micro, Inc, LM3S2651 Datasheet - Page 153

• Manufacturer Part Number: LM3S2651
• Description: Lm3s2651 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
8.6
July 25, 2008
Bit/Field
31:2
1
0
RO
RO
31
15
0
0
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
PMISC
AMISC
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
R/W1C
Type
RO
RO
RO
26
10
0
0
Reset
0x0
RO
RO
25
0
9
0
0
0
reserved
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 151) is also
cleared when the PMISC bit is cleared.
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S2651 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
R/W1C
PMISC
RO
17
0
1
0
AMISC
R/W1C
RO
16
0
0
0
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