LM3S2651 Luminary Micro, Inc, LM3S2651 Datasheet - Page 314

• Manufacturer Part Number: LM3S2651
• Description: Lm3s2651 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Universal Asynchronous Receivers/Transmitters (UARTs)
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
314
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / F
where F
You must choose the divisor so that 1.42 MHz < F
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note:
RO
RO
30
14
0
0
ILPDVSR
reserved
RO
RO
29
13
0
0
Name
IrLPBaud16
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
RO
RO
28
12
0
0
reserved
is nominally 1.8432 MHz.
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
IrLPBaud16
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
reserved
R/W
RO
23
0
7
0
IrLPBaud16
R/W
RO
22
0
6
0
< 2.12 MHz, which results in a low-power
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
ILPDVSR
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
July 25, 2008
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0