LM3S2918 Luminary Micro, Inc, LM3S2918 Datasheet - Page 381

• Manufacturer Part Number: LM3S2918
• Description: Lm3s2918 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

15.2.3
15.2.3.1 I
15.2.3.2 I
15.2.4
July 26, 2008
Interrupts
The I
■
■
■
■
There is a separate interrupt signal for the I
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
The I
receive), or when an error occurs during a transaction. To enable the I
must write a '1' to the I
is met, software must check the ERROR bit in the I
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I
The slave module generates interrupts as it receives requests from an I
I
determines whether the module should write (transmit) or read (receive) data from the I
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I
Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I
Loopback Operation
The I
is accomplished by setting the LPBK bit in the I
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
System Clock
2
2
2
C slave interrupt, write a '1' to the I
C Master Interrupts
C Slave Interrupts
Master transaction completed
Master transaction error
Slave transaction received
Slave transaction requested
50Mhz
2
2
2
2
2
C Master Raw Interrupt Status (I2CMRIS) register.
C Slave Raw Interrupt Status (I2CSRIS) register.
C can generate interrupts when the following conditions are observed:
C master module generates an interrupt when a transaction completes (either transmit or
C modules can be placed into an internal loopback mode for diagnostic or debug work. This
Timer Period
0x18
2
C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
Standard Mode
100 Kbps
2
C Slave Interrupt Mask (I2CSIMR) register. Software
Preliminary
Timer Period
2
0x06
C master and I
2
C Master Configuration (I2CMCR) register. In
2
C Master Control/Status (I2CMCS) register to
Fast Mode
357 Kbps
2
C slave modules. While both modules
2
2
C Slave Control/Status
C master interrupt, software
2
C master. To enable the
LM3S2918 Microcontroller
2
C Master Interrupt
2
2
C Slave
C Slave
381