LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 404

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Universal Asynchronous Receivers/Transmitters (UARTs)
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
404
Bit/Field
31:11
3:0
10
RO
RO
9
8
7
6
5
4
31
15
0
0
RO
RO
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
30
14
0
0
reserved
RO
RO
29
13
reserved
reserved
0
0
OEMIS
BEMIS
PEMIS
RXMIS
FEMIS
RTMIS
TXMIS
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
OEMIS
RO
RO
26
10
0
0
BEMIS
RO
RO
Reset
25
0x00
0
9
0
0
0
0
0
0
0
0
0
Preliminary
PEMIS
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FEMIS
RO
RO
23
0
7
0
RTMIS
RO
RO
22
0
6
0
TXMIS
RO
RO
21
0
5
0
RXMIS
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
June 02, 2008
RO
RO
16
0
0
0