LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 504

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
17.3
17.3.1
17.3.2
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host controller can begin device enumeration. If the device is disconnected while a session is in
progress, a disconnect interrupt is generated.
Initialization and Configuration
The initial configuration in all cases requires that the processor enable the USB controller before
setting any registers. The next step is to enable the USB PLL so that the correct clocking is provided
to the USB controller’s physical layer interface (PHY). To ensure that voltage is not supplied to the
bus incorrectly, the external power control signal, USB0EPEN, should be de-asserted on start up.
This requires setting the USB0EPEN and USB0PFLT pins to be controlled by the USB controller and
not have their default GPIO behavior.
The USB controller provides a method to set the current operating mode of the USB controller. This
register should be written with the desired default mode so that the controller can respond to external
USB events.
Pin Configuration
When using the device controller portion of the USB controller in a system that also provides host
functionality, the power to VBUS must be disabled to allow the external host controller to supply
power. Usually, the USB0EPEN signal is used to control the external regulator and should be
de-asserted to avoid having two devices driving the USB0VBUS power pin on the USB connector.
When the USB controller is acting as a host, it is in control of two signals that are attached to an
external voltage supply that provides power to VBUS. The host controller uses the USB0EPEN signal
to enable or disable power to the USB0VBUS pin on the USB connector. There is also an input pin,
USB0PFLT, which provides feedback when there has been a power fault on VBUS. The USB0PFLT
signal can be configured to either automatically de-assert the USB0EPEN signal to disable power,
and/or it can generate an interrupt to the main processor to allow it to handle the power fault condition.
The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB
controller. The controller also provides interrupts on device insertion and removal to allow the host
controller code to respond to these external events.
Endpoint Configuration
In order to start communication on host or device mode, the endpoint registers must first be
configured. In Host mode, this provides a connection between an endpoint register and an endpoint
on a device. In Device mode, this provides the setup for a given endpoint before enumerating to
the host controller.
In both cases, the endpoint 0 configuration is limited as this is a fixed function, fixed FIFO size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 bytes with the first 64 bytes in use by endpoint
0. The endpoint’s FIFO does not have to be the same size as the maximum packet size in all cases
Preliminary
June 02, 2008