IDT72V285L10TF IDT, Integrated Device Technology Inc, IDT72V285L10TF Datasheet - Page 23

• Manufacturer Part Number: IDT72V285L10TF
• Description: IC FIFO SS 65536X18 10NS 64STQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V285L10TF

• Function: Asynchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V285L10TF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/
OR assertion to vary by one cycle between FIFOs. In IDT Standard mode,
such problems can be avoided by creating composite flags, that is, ANDing
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 32,768 and 65,536 for the IDT72V285 with an 18-bit bus width.
In FWFT mode, the FIFOs can be connected in series (the data outputs of one
FIFO connected to the data inputs of the next) with no external logic necessary.
The resulting configuration provides a total depth equivalent to the sum of the
depths associated with each single FIFO. Figure 20 shows a depth expansion
using two IDT72V275/72V285 devices.
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
The IDT72V275 can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all FIFOs
For an empty expansion configuration, the amount of time it takes for OR of
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
TM
72V275
72V285
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
23
0
n
- Qm
EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
devices. D
from each device form a 36-bit wide output bus. Any word width can be attained
by adding additional IDT72V275/72V285 devices.
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
Note that extra cycles should be added for the possibility that the t
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
The "ripple down" delay is only noticeable for the first word written to an empty
The first free location created by reading from a full depth expansion
Figure 19 demonstrates a width expansion using two IDT72V275/72V285
72V275
72V285
FIFO
IDT
#2
0
- D
17
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
from each device form a 36-bit wide input bus and Q
Qm
(N – 1)*(4*transfer clock) + 3*T
+1
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
RCLK
RCLK
is the RCLK period.
4512 drw 22
GATE
SKEW3
(1)
0
-Q
17