CY7C433-10AXC Cypress Semiconductor Corp, CY7C433-10AXC Datasheet - Page 11

• Manufacturer Part Number: CY7C433-10AXC
• Description: IC ASYNC FIFO MEM 4KX9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C433-10AXC

• Function: Asynchronous
• Memory Size: 36K (4K x 9)
• Data Rate: 50MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Architecture
The
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of dual-port
RAM cells), a read pointer, a write pointer, control signals (W, R,
XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write opera-
tions to be independent of each other, which is necessary to
achieve truly asynchronous operation of the inputs and outputs.
A second benefit is that the time required to increment the read
and write pointers is much less than the time required for data
propagation through the memory, which is the case if memory is
implemented using the conventional register array architecture.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W)
must be HIGH t
of MR for a valid reset cycle. If reading from the FIFO after a reset
cycle is attempted, the outputs are in the high impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs t
LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW
t
Half Full. Therefore, the HF is active once the FIFO is filled to
half its capacity plus one word. HF will remain LOW while less
than one half of total memory is available for writing. The
LOW-to-HIGH transition of HF occurs t
of R when the FIFO goes from half full +1 to half full. HF is
available in standalone and width expansion modes. FF goes
LOW t
the last available location is filled. Internal logic prevents
overrunning a full FIFO. Writes to a full FIFO are ignored and the
write pointer is not incremented. FF goes HIGH tRFF after a read
from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q
between read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high impedance state and remain such
until a write is performed. Reads to an empty FIFO are ignored
and do not increment the read pointer. From the empty condition,
the FIFO can be read t
Document #: 38-06001 Rev. *C
WHF
after the falling edge of W following the FIFO actually being
WFF
CY7C419,
after the falling edge of W, during the cycle in which
RPW
0
to Q
/t
CY7C420/1,
WPW
WEF
8
) are in a high impedance condition
before and t
after a valid write.
0
–D
8
) t
SD
CY7C424/5,
before and t
RMR
RHF
after the rising edge
after the rising edge
WEF
after the first
CY7C428/9,
HD
after the
The retransmit feature is beneficial when transferring packets of
data. It enables the receiver to acknowledge receipt of data and
retransmit, if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. R and W must both be HIGH while and t
retransmit is LOW. With every read cycle after retransmit, previ-
ously accessed data and not previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Full, Half Full, and Empty flags are governed by the
relative locations of the read and write pointers and are updated
during a retransmit cycle. Data written to the FIFO after activation
of RT are also transmitted. FIFO, up to the full depth, can be
repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to V
expanded in width to provide word widths greater than nine in
increments of nine. During width expansion mode, all control line
inputs are common to all devices, and flag outputs from any
device can be monitored.
Depth Expansion Mode
Depth expansion mode
when, during a MR cycle, Expansion Out (XO) of one device is
connected to Expansion In (XI) of the next device, with XO of the
last device connected to XI of the first device. In the depth
expansion mode the First Load (FL) input, when grounded,
indicates that this part is the first to be loaded. All other devices
must have this pin HIGH. To enable the correct FIFO, XO is
pulsed LOW when the last physical location of the previous FIFO
is written to and pulsed LOW again when the last physical
location is read. Only one FIFO is enabled for read and one for
write at any given time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When expanding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a
composite EF is created by ORing the EFs together. HF and RT
functions are not available in depth expansion mode.
Use of the Empty and Full Flags
To achieve maximum frequency, the flags must be valid at the
beginning of the next cycle. However, because they can be
updated by either edge of the read or write signal, they must be
valid by one-half of a cycle. Cypress FIFOs meet this
requirement; some competitors’ FIFOs do not.
The reason for why the flags should be valid by the next cycle is
complex. The “effective pulse width violation” phenomenon can
occur at the full and empty boundary conditions, if the flags are
not properly used. The empty flag must be used to prevent
reading from an empty FIFO and the full flag must be used to
prevent writing into a full FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored
by the FIFO, and nothing happens. Next, a single word is written
(see
CY7C419/21/25/29/33
Figure 13
on page 12
CC
. FIFOs can be
Page 11 of 17
)
is entered
RTR
after
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