TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet
TS68EN360MAB
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TS68EN360MAB Summary of contents
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Features CPU32+ Processor (4.5 MIPS at 25 MHz) • – 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32) – Background Debug Mode – Byte-misaligned Addressing Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 ...
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Introduction 1.1 QUICC Architecture Overview The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB). The TS68302 is an ...
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Pin Assignments Figure 2- Note: 2113B–HIREL–06/05 241-lead Pin Grid Array (PGA) PA15 PA12 PA9 PA6 PA3 PA2 PB17 PB15 D2 D0 ...
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Figure 2-2. 240-lead Cerquad 180 170 GNDs1 181 CAS3 CAS2 Vcc CAS1 GND CAS0 FREEZE DS GND 190 R/W NC3 Vcc DSACK0 GND DSACK1 GND PRTY3 PRTY2 GND 200 Vcc PRTY1 PRTY0 IPIPE0 AS GNDs2 IPIPE1 Vcc NC2 BCLRO 210 ...
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Signal Description 3.1 Functional Signal Group Figure 3-1. QUICC Functional Signal Groups L1TXDB/RXD3/PA4 L1RXDB/TXD3/PA5 L1TXDA/RXD4/PA6 L1RXDA/TXD4/PA7 TIMERs/SCCs/SIs/CLOCKs/BRG TIN1/L1RCLKA/BRGO1/CLK1/PA8 BRGCLK1/TOUT1/CLK2/PA9 TIN2/L1TCLKA/BRGO2/CLK3/PA10 TOUT2/CLK4/PA11 TIN3/BRGO3/CLK5/PA12 BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13 TIN4/BRGO4/CLK7/PA14 L1TCLKB/TOUT4/CLK8/PA15 RRJCT1/SPISEL/PB0 RSTRT2/SPICLK/PB1 RRJCT2/SPIMOSI(SPITXD)/PB2 BRGO4/SPIMISO(SPIRXD)/PB3 DREQ1/BRGO1/PB4 DACK1/BRGO2/PB5 DONE1/SMTXD1/PB6 DONE2/SMRXD1/PB7 DREQ2/SMSYN1/PB8 DACK2/SMSYN2/PB9 L1CLKOB/SMTXD2/PB10 L1CLKOA/SMRXD2/PB11 L1ST1/RTS1/PB12 L1ST2/RTS2/PB13 ...
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Signal Index Table 1. System Bus Signal Index (Normal Operation) Group Signal Name Address Bus Address Bus/Byte Write Address Enables Function Codes Data Bus Data Data Bus Parity Parity Parity ...
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Table 1. System Bus Signal Index (Normal Operation) (Continued) Group Signal Name Data and Size Acknowledge Address Strobe Data Strobe Bus Control Size Read/Write Output Enable Address Multiplex Interrupt Request Level 7-1 Interrupt Control Autovector/Interrupt Acknowledge 5 Soft Reset Hard ...
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Table 1. System Bus Signal Index (Normal Operation) (Continued) Group Signal Name Three-State Test Clock Clock and Test Test Mode Select (Cont’d) Test Data In Test Data Out Test Reset Clock Synthesizer Power Clock Synthesizer Ground Clock Out Power Clock ...
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Table 3-1. Peripherals Signal Index Group Signal Name Receive Data Transmit Data Request to Send Clear to Send Carrier Detect SCC Receive Start Receive Reject Clocks DMA Request IDMA DMA Acknowledge DMA Done Timer Gate TIMER Timer Input Timer Output ...
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Table 3-1. Peripherals Signal Index (Continued) Group Signal Name SI Receive Data SI Transmit Data SI Receive Clock SI Transmit Clock SI Transmit Sync Signals SI SI Receive Sync Signals IDL Interface Request SI Output Clock SI Data Strobes Baud ...
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Detailed Specification This specification describes the specific requirements for the microcontroller TS68EN360 - 25 MHz and 33 MHz in compliance with MIL-STD-883 class B or Atmel standard screening. 5. Applicable Documents 1. MIL-STD-883: test methods and procedures for electronics ...
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This device contains protective circuitry against damage due to high static voltages or electrical fields; however advised that normal precautions be taken to avoid application of any volt- ages higher than maximum-rated voltages to this high-impedance circuit. Reliability ...
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An approximate relationship between P P Solving Equations (1) and (2) for K gives where constant pertaining to the particular part. K can be determined from Equation (3) by measuring P T can be ...
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Static Characteristics The electrical specifications in this document are preliminary. (See numbered notes) Table 7-1. Static Characteristics – GND = 0 V Characteristic Input High Voltage (except EXTAL) Input Low Voltage (5V Part) Input Low Voltage (Part Only; PA8-15, ...
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Figure 7-1. Drive Levels and Test Points For AC Specifications CLKOUT 2.0V OUTPUTS (1) VALID OUTPUT n 0.8V OUTPUTS (2) INPUTS (3) INPUTS (4) ALL SIGNALS (5) Notes: 1. This output timing is applicable to all parameters specified relative to ...
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AC Power Dissipation Table 7-2. Typical Current Drain Mode of Operation (1) (2) Normal mode (Rev A and Rev B ) (3) Normal Mode (Rev C and Newer) Normal Mode Low Power Mode Low Power Mode Low Power Mode ...
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AC Electrical Specifications Control Timing Table 7-4. GND = -55 to +125°C. The electrical specifications in this document are preliminary (See DC C 7-2) Number Characteristic System Frequency Crystal Frequency On-Chip VCO System Frequency ...
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Figure 7-2. (INPUT) CLKO1 (OUTPUT) CLKO2 (OUTPUT) 7.6 External Capacitor For PLL Table 7-5. GND = -55 to +125°C. The electrical specifications in this document are preliminary Characteristic PLL External Capacitor (XFC to ...
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Bus Operation AC Timing Specifications Table 7-6. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-3 to Number Characteristic 6 CLKO1 High to Address, FC, ...
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Table 7-6. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-3 to Figure Number Characteristic 20 CLKO1 High to R/W Low (10) 21 R/W High to ...
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Table 7-6. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-3 to Number Characteristic R/W Width Asserted (Fast Termination Write or 46A Read) 47A Asynchronous Input ...
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Table 7-6. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-3 to Figure Number Characteristic 83 DSCLC Hold Time 84 DSO Delay Time 85 DSCLK Cycle ...
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Figure 7-3. Note: 2113B–HIREL–06/05 Read Cycle S0 S1 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT (OUTPUT) DS (OUTPUT) CSx (OUTPUT) OE (OUTPUT R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) 31A D31-D0 (INPUT) BERR, ...
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Figure 7-4. TS68EN360 24 Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 9 14B AS (OUTPUT) DS (OUTPUT) CSx (OUTPUT) OE (OUTPUT) 18 46A ...
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Figure 7-5. Note: 2113B–HIREL–06/05 Read Cycle (With Parity Check, PBEE = CLKO1 (OUTPUT) 6 A31-A0, FC3-FC0, SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT (OUTPUT) DS (OUTPUT) CSx (OUTPUIT) OE (OUTPUT R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) ...
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Figure 7-6. TS68EN360 26 SRAM: Read Cycle (TRLX = CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT (OUTPUT) 11A DS (OUTPUT) 9B CSx (OUTPUT) 21A OE (OUTPUT) 18 R/W (OUTPUT) DSACK0 ...
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Figure 7-7. CLKO1 (OUTPUT) A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) AS (OUTPUT) DS (OUTPUT) IACKx (OUTPUT) OE (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) D31-D0 (INPUT) Note: 2113B–HIREL–06/05 CPU32+ IACK Cycle * 0-2 CLOCKS ...
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Figure 7-8. Note: TS68EN360 28 Write Cycle S0 S1 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT (OUTPUT (OUTPUT) CSn (OUTPUT) 22 WEn (OUTPUT) 20 R/W (OUTPUT) DSACK0 (I/O) 31A DSACK1 (I/O) 55 D31-D0 (OUTPUT) ...
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Figure 7-9. Figure 7-10. SRAM: Fast Termination Write Cycle (CSNTQ = 1) 2113B–HIREL–06/05 Fast Termination Write Cycle S0 S1 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) AS (OUTPUT) 9 CSx (OUTPUT) DS (OUTPUT) WEx (OUTPUT) 20 R/W R/W ...
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Figure 7-11. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0) Note: Figure 7-12. ASYNC Bus Arbitration – IDLE Bus Case CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) (OUTPUT) (INPUT) (OUTPUT) BGACK (INPUT) BCLRO (OUTPUT) TS68EN360 30 S0 ...
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Figure 7-13. ASYNC Bus Arbitration – Active Bus Case Figure 7-14. SYNC Bus Arbitration – IDLE Bus Case 2113B–HIREL–06/ CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) 47A ...
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Figure 7-15. SYNC Bus Arbitration – Active Bus Case S0 CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) BR (INPUT) BG (OUTPUT) BGACK (INPUT) BCLRO (OUTPUT) Figure 7-16. Configuration and Clock Mode ...
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Figure 7-17. Show Cycle Figure 7-18. Background Debug Mode FREEZE Timing Figure 7-19. Background Debug Mode Serial Port Timing 2113B–HIREL–06/05 S0 S41 S42 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) 18 R/W (OUTPUT (OUTPUT (OUTPUT) 70 D31-D0 ...
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Figure 7-20. DRAM: Normal Read Cycle (Internal Mux, TRLX = 0) S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) AS (OUTPUT) 9 RASx (OUTPUT) CAS3-CAS0 (OUTPUT) OE (OUTPUT R/W (OUTPUT) DSACK1,0 (I/O) D31ÐD0 (INPUT) PARITY3-PARITY0 (INPUT) D31-D0 (INPUT) Note: TS68EN360 ...
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Bus Operation – DRAM Accesses AC Timing Specification Table 7-7. GND = -55 to +125°C. The electrical specifications in this document are preliminary (See DC 7-20 to Figure 7-24) Number Characteristic 100 RASx Asserted ...
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Figure 7-21. DRAM: Normal Write Cycle Note: TS68EN360 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT (OUTPUT) 9 100 RASx 101 (OUTPUT) CAS3-CAS0 (OUTPUT) WEx (OUTPUT) 20 115 R/W (OUTPUT) DSACK1,0 (I/O) D31-D0 (OUTPUT) 23 PARITY0-PARITY3 (OUTPUT) All ...
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Figure 7-22. DRAM: Refresh Cycle Note: Figure 7-23. DRAM: Page Mode – Page-Hit Note: 2113B–HIREL–06/ CLKO1 (OUTPUT) A31-A0 (OUTPUT) CAS3-CAS0 (OUTPUT) 12 RASx (OUTPUT) 12A RASx (OUTPUT) PAGE MODE NOT IN PAGE MODE All timing is shown with ...
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Figure 7-24. DRAM: Page Mode – Page-Miss (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) CAS3-CAS0 (OUTPUT) (OUTPUT) Note: TS68EN360 CLKO1 6A 6A A31-A0 INTERNAL MUX RASn 122 123 AMUX 120 EXTERNAL MUX All timing is ...
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Bus Type Slave Mode Bus Arbitration AC Electrical Specifications Table 7-8. GND = -55 to +125°C. The electrical specifications in this document are preliminary (See DC C 7-25) Number Characteristic 231 Address, Transfer ...
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Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical Specifications Table 7-9. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-26 to Number Characteristic ...
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Figure 7-26. TS68040 Internal Registers Read Cycles C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) 252 TS (INPUT) D31-D0 (040 WRITE) (INPUT) TA (OUTPUT) TBI (OUTPUT) Notes: 1. Three wait states are inserted when reading the SIM, dual-port RAM, ...
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Figure 7-28. TS68040 IACK Cycles (Vector Driven) CLKO1 (OUTPUT) A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) (INPUT) D31-D0 (OUTPUT) (OUTPUT) TBI (OUTPUT) IACK7-1 (OUTPUT) Notes: Figure 7-29. TS68040 IACK Cycles (No Vector Driven) Note: TS68EN360 251 253 ...
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Bus Type SRAM/DRAM Cycles AC Electrical Specifications Table 7-10. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-30 to Number Characteristic 280 Address Valid ...
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Figure 7-30. TS68040 SRAM Read/Write Cycles (TSS40 = 0, CSNT40 = 0) Note: TS68EN360 44 C1 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3- BADD2 (OUTPUT) 252 TS (INPUT) 282 CSx (OUTPUT) TA (OUTPUT) TBI (OUTPUT) BKPTO (OUTPUT) ...
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Figure 7-31. TS68040 SRAM Read/Write Cycles (TSS40 = 1, CSNT40 = 1) 2113B–HIREL–06/05 C1 CLKO1 (OUTPUT) 251 TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3- BADD2 (OUTPUT) 252 TS (INPUT) CSn (OUTPUT) 286 TA (OUTPUT) TBI (OUTPUT) BKPTO (OUTPUT) TEA (INPUT) ...
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Figure 7-32. External TS68040 DRAM Cycles Timing Diagram (WRITE CYCLE TS68EN360 46 C1 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3- BADD2 (OUTPUT) 252 TS (INPUT) RASx (OUTPUT) CAS3- CAS0 (OUTPUT) 121 298 AMUX (OUTPUT) 297 WE OUTPUT) ...
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Figure 7-33. External TS68040 DRAM Burst Cycles Timing Diagram C1 CLKO1 (OUTPUT) TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3- BADD2 (OUTPUT) TS (INPUT) 282 RASx (OUTPUT) CAS3- CAS0 (OUTPUT) AMUX (OUTPUT) WE (WRITE CYCLE OUTPUT) 293 TA (OUTPUT) TBI (OUTPUT) ...
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Figure 7-34. External TS68040 Parity Bit Checking Timing Diagram D31-D0 (INPUT) PRTY3- PRTY0 (OUTPUT) CLKO1 (OUTPUT) TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) BADD3- BADD2 (OUTPUT) TS (INPUT) TA (OUTPUT) D31-D0, (INPUT) PRTY3- PRTY0 (INPUT) PERR (OUTPUT) TS68EN360 48 212 (a) Generation ...
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IDMA AC Electrical Specifications Table 7-11. GND = -55 to +125°C.The electrical specifications in this document are preliminary DC C (See Figure 7-35 and Number Characteristic 1 CLKO1 Low to DACK, DONE Asserted 2 ...
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Figure 7-35. IDMA Signal Asynchronous Timing Diagram S0 S1 CLKO1 (OUTPUT) 4 DREQ (INPUT) AS (OUTPUT) DACK (OUTPUT) DONE (OUTPUT) DONE (INPUT) Figure 7-36. IDMA Signal Synchronous Timing Diagram S0 CLKO1 (OUTPUT) 12 DREQ (INPUT) AS (OUTPUT) DACK (OUTPUT) DONE ...
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PIP/PIO Electrical Specifications Table 7-12. GND = -55 to +125°C.The electrical specifications in this document are preliminary DC C (See Figure 7-37 to Number Characteristic 21 Data-In Setup Time to STBI Low 22 Data-In ...
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Figure 7-38. PIP Tx (Interlock Mode) DATA IN STRBI (INPUT) STRBO (OUTPUT) Figure 7-39. PIP Tx (Pulse Mode) DATA IN STBI (INPUT) STBO (OUTPUT) TS68EN360 2113B–HIREL–06/05 ...
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Figure 7-40. PIP Tx (Pulse Mode) DATA OUT STBO (OUTPUT) STBI (INPUT) Figure 7-41. Parallel I/O Data-in/Data-out Timing Diagram CLKO1 (OUTPUT) DATA IN DATA OUT 7.14 Interrupt Controller AC Electrical Specifications Table 7-13. GND = ...
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Figure 7-42. Interrupts Timing Diagram Port C (INPUT) Figure 7-43. Slave Mode: Interrupts Timing Diagram 7.15 BAUD Rate Generator AC Electrical Specifications Table 7-14. GND = -55 to +125 DC C 7-44) Number Characteristic 50 ...
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Timer Electrical Specifications Table 7-15. GND = -55 to +125°C. The electrical specifications in this document are preliminary (See DC C 7-45) Number Characteristic 61 TIN/TGATE Rise and Fall Time 62 TIN/TGATE Low Time ...
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SI Electrical Specifications Table 7-16. GND = -55 to +125°C.The electrical specifications in this document are preliminary DC, C (See Figure 7-46 to Number Characteristic (1)(3) 70 L1RCLK, L1TCLK Frequency (DCS = 0) (1) 71 ...
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Figure 7-46. SI Receive Timing with Normal Clocking (DSC = 0) L1RCLK ( (INPUT) L1RCLK (FE =1, (INPUT) 75 L1RSYNC (INPUT) 73 L1RXD (INPUT) L1ST (4-1) (OUTPUT) 2113B–HIREL–06/ RFCD = 1 ...
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Figure 7-47. SI Receive Timing with Double Speed Clocking (DSC = 1) L1RCLK ( (INPUT) L1RCLK ( (INPUT) 75 L1RSYNC (INPUT) 73 L1RXD (INPUT) L1ST (4-1) (OUTPUT) L1CLKO (OUTPUT) 84 ...
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Figure 7-48. SI Transmit Timing with Normal Clocking (DSC = 0) L1TCLK ( (INPUT) L1TCLK ( (INPUT) 75 L1TSYNC (OUTPUT) 73 80A L1TXD (INPUT) 80 L1ST (4-1) (OUTPUT) 2113B–HIREL–06/05 72 ...
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Figure 7-49. SI Transmit Timing with Double Speed Clocking (DSC = 1) L1RCLK ( (INPUT) L1RCLK ( (INPUT) 75 L1TSYNC (INPUT) 73 80A L1TXD BIT0 (OUTPUT) 80 78A L1ST (1-4) ...
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SCC in NMSI Mode-external Clock Electrical Specifications Table 7-17. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-51 to Number Characteristic (1) 100 RCLK1 and ...
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Figure 7-51. SCC NMSI Receive 102 RCLK1 106 RXD1 (INPUT) CD1 (INPUT) CD1 (SYNC- INPUT) Figure 7-52. SCC NMSI Transmit 102 TCLK1 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (INPUT) CTS1 (SYNC- INPUT) TS68EN360 62 102 101 100 107 102 101 100 ...
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Figure 7-53. HDLC BUS Timing 102 TCLK1 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (ECHO INPUT) 2113B–HIREL–06/05 102 101 100 103 104 107 105 TS68EN360 104 63 ...
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Ethernet Electrical Specifications Table 7-19. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-54 to Number Characteristic 120 CLSN Width High 121 RCLK1 Rise/Fall Time ...
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Figure 7-55. Ethernet Receive Timing RCLK1 RXD1 (INPUT) RENA (CD1) (INPUT) Figure 7-56. Ethernet Transmit Timing 128 TCLK1 (NOTE 1) 131 TXD1 (OUTPUT) 133 TENA (RTS1) (OUTPUT) RENA (CD1) (INPUT) (NOTE 2) Notes: 1. Transmit clock invert (TCI) bit in ...
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Figure 7-57. CAM Interface Receive Start Timing RCLK1 RXD1 0 (INPUT) START FRAME DELIMITER RSTRT (OUTPUT) Note: Figure 7-58. CAM Interface Reject Timing Note: Figure 7-59. SDACK Timing Diagram Note: TS68EN360 Valid for the ethernet protocol only. ...
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SMC Transparent Mode Electrical Specifications Table 7-20. GND = -55 to +125°C. The electrical specifications in this document are preliminary (See DC C 7-60) Number Characteristic (1) 150 SMCLK Clock Period 151 SMCLK Width ...
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SPI Master Electrical Specifications Table 7-21. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-61 and Number Characteristic 160 Master Cycle Time 161 Master Clock ...
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Figure 7-62. SPI Master ( 7.23 SPI Slave Electrical Specifications Table 7-22. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-63 and Number Characteristic ...
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Figure 7-63. SPI Slave ( Figure 7-64. SPI Slave ( TS68EN360 70 SPISEL INPUT SPICLK CI=0 INPUT 173 SPICLK CI=1 INPUT 173 180 177 SPIMISO MSB OUT DATA OUTPUT 176 175 SPIMOSI MSB IN DATA INPUT ...
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JTAG Electrical Specifications Table 7-23. GND = -55 to +125°C. The electrical specifications in this document are preliminary DC C (See Figure 7-65 and Number Characteristic TCK Frequency of Operation 1 TCK Cycle Time ...
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Figure 7-67. Boundary Scan (JTAG) Timing Diagram OUTPUTS OUTPUTS Figure 7-68. Test Access Port Timing Diagram TS68EN360 72 TCK (INPUT DATA INPUTS 8 DATA 9 DATA 8 DATA OUTPUTS TCK (INPUT TDI TMS (INPUT) 12 TDO ...
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Functional Description 8.1 CPU32+ Core The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path ...
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The CP provides the communication features of the QUICC. Included are a RISC processor, four SCCs, two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot assigner, three parallel ports, a parallel interface port, four ...
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Upgrading Designs from the TS68302 Since the QUICC is a next-generation TS68302, many designers currently using the TS68302 may wish to use the QUICC in a follow-on design. The following paragraphs briefly discuss this endeavor in terms of architectural ...
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The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block on the TS68302. The register addresses within that memory map are different • The code used to initialize the system integration features of the TS68302 ...
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Package Mechanical Data 11.1 241-pin – PGA (top view) T (BOTTOM VIEW 2113B–HIREL–06/05 Inches Dim Min Max A 1.840 1.880 C 0.110 0.140 D 0.016 0.020 E 0.045 0.055 F 0.045 0.055 G 0.100 BASIC K ...
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CERQUAD U 180 181 240 1 –M– TIPS 0.25 (0.010) T L–N M VIEW AE DATUM –H– PLANE Notes: 1. Dimensioning and tolerancing per ASME Y 14.5, 1994. 2. Controlling dimension: millimeter. 3. Datum ...
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... Ordering Information 12.1 Hi-REL Product Commercial Atmel Part-Number TS68EN360MRB/Q25L MIL-PRF-38535 TS68EN360MRB/Q33L MIL-PRF-38535 TS68EN360MR1B/Q25L MIL-PRF-38535 TS68EN360MR1B/Q33L MIL-PRF-38535 TS68EN360MAB/Q25L MIL-PRF-38535 TS68EN360MAB/Q33L MIL-PRF-38535 12.2 Standard Product Commercial Atmel Part-Number TS68EN360VR25L Atmel Standard TS68EN360MR25L Atmel Standard TS68EN360VA25L Atmel Standard TS68EN360MA25L Atmel Standard TS68EN360VR33L Atmel Standard TS68EN360MR33L Atmel Standard ...
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Document Revision History Table 13-1 Table 13-1. Revision Number TS68EN360 80 provides a revision history for this hardware specification. Revision History Date 2113B 04/2005 2113A 03/2002 Substantive Change(s) Cerquad Package Change. See page 77 Initial Revision 2113B–HIREL–06/05 ...
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Table of Contents Features .................................................................................................... 1 Description ............................................................................................... 1 Screening/Quality 1 Introduction .............................................................................................. 2 2 Pin Assignments ...................................................................................... 3 3 Signal Description ................................................................................... 5 4 Detailed Specification ............................................................................ 11 5 Applicable Documents .......................................................................... 11 6 Quality Conformance Inspection .......................................................... 13 ...
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Functional Description .......................................................................... 73 9 Preparation for Delivery ........................................................................ 76 10 Handling .................................................................................................. 76 11 Package Mechanical Data ..................................................................... 77 12 Ordering Information ............................................................................. 79 13 Document Revision History .................................................................. 80 TS68EN360 ii 7.13 PIP/PIO Electrical Specifications ..........................................................................51 7.14 ...
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... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...