TS80C51RA2 Atmel Corporation, TS80C51RA2 Datasheet
TS80C51RA2
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TS80C51RA2 Summary of contents
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... In the power-down mode the RAM is saved and all other functions are inoperative and Industrial (- High Performance 8-bit Microcontroller TS80C51RA2 TS80C51RD2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 Rev. 4188A–8051–10/02 1 ...
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... PDIL40 PLCC44 VQFP44 1.4 TS80C51RA2 TS80C51RD2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 PLCC68 VQFP64 1.4 TS80C51RD2 TS83C51RD2 TS87C51RD2 Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN EA/VPP (3) RD (3) WR TS8xC51Rx2 2 ROM (bytes) EPROM (bytes 16k 0 32k 0 64k 0 0 16k 0 32k 0 64k ROM (bytes) ...
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SFR Mapping 4188A–8051–10/02 The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3, P4, P5 • Timer registers: ...
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Bit Non Bit addressable addressable 0/8 1/9 CH F8h 0000 0000 B F0h 0000 0000 P5 bit CL addressable E8h 0000 0000 1111 1111 ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 PSW D0h 0000 0000 T2CON ...
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Pin Configuration P1 P1.1 / T2EX P1.2 3 P1.3 4 P1.4 5 P1 P1.7 RST 9 P3.0/RxD 10 PDIL/ P3.1/TxD 11 12 P3.2/INT0 CDIL40 P3.3/INT1 13 14 P3.4/T0 15 P3.5/T1 P3.6/WR 16 ...
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TS8xC51Rx2 6 4188A–8051–10/02 ...
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Pin Number Mnemonic DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 P1.0-P1.7 1-8 2 P2.0-P2.7 ...
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Pin Number Mnemonic DIL LCC VQFP 1 Reset 9 10 ALE/PROG 30 33 PSEN XTAL1 19 21 XTAL2 18 20 Pin Description for 64/68 pin Packages ...
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Table 2. 64/68 Pin Packages Configuration Pin VSS VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 TS8xC51Rx2 PLCC68 SQUARE VQFP64 ...
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TS8xC51Rx2 10 Pin P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET ALE/PROG PSEN EA/VPP XTAL1 XTAL2 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 PLCC68 SQUARE VQFP64 1 ...
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TS80C51Rx2 Enhanced Features X2 Feature Description 4188A–8051–10/02 In comparison to the original 80C52, the TS8xC51Rx2 implements some new features, which are : • The X2 option. • The Dual Data Pointer. • The extended RAM. • The Programmable Counter Array ...
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Figure 2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode TS8xC51Rx2 12 X2 Mode The X2 bit in the CKCON register (Table 3) allows to switch from 12 clock cycles per instruction to 6 clock cycles and ...
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Dual Data Pointer Register Figure 3. Use of Dual Pointer 7 0 DPS AUXR1(A2H) 4188A–8051–10/02 The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure ...
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Application TS8xC51Rx2 14 Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer ...
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Expanded RAM (XRAM) 4188A–8051–10/02 The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH ...
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Figure 4. Internal and External Data Memory Address FF(RA, RB, RC)/2FF (RD) XRAM 256 bytes 00 TS8xC51Rx2 16 MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located ...
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Timer 2 Auto-reload Mode 4188A–8051–10/02 TS80C51RX2 The timer 2 in the 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade controlled by T2CON register (See Table 6) ...
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Figure 5. Auto-reload Mode Up/Down Counter (DCEN = 1) XTAL1 F XTAL Programmable Clock-Output TS8xC51Rx2 18 (: mode) :12 F OSC T2 (DOWN COUNTING RELOAD VALUE) FFh (8-bit) TL2 (8-bit) RCAP2L (8-bit) (UP COUNTING RELOAD VALUE) In the ...
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Figure 6. Clock-Out Mode C/ XTAL1 T2 T2EX 4188A–8051–10/ possible to use timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not ...
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TS8xC51Rx2 20 Table 6. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer ...
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Table 7. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Programmable Counter Array PCA TS8xC51Rx2 22 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as ...
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Figure 7. PCA Timer/Counter Fosc /12 Fosc / 4 T0 OVF P1.2 Idle 4188A–8051–10/02 CIDL CPS1 CPS0 WDTE CF CR CCF4 CCF3 CCF2 CCF1 CCF0 Table 8. CMOD: PCA Counter Mode Register CMOD Address 0D9H CIDL Reset value Symbol Function ...
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TS8xC51Rx2 24 The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 8). • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables ...
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Figure 8. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 ECF 4188A–8051–10/02 The PCA interrupt system is shown in Figure CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 PCA Modules: ...
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CCAPM0=0DAH CCAPM1=0DBH CCAPMn Address CCAPM2=0DCH CCAPM3=0DDH CCAPM4=0DEH Reset value Symbol Function - Not implemented, reserved for future use. ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables ...
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Table 11. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn ...
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PCA Capture Mode Figure 9. PCA Capture Mode CF Cex.n ECOMn TS8xC51Rx2 28 Table 14. CH: PCA Counter High CH Address 0F9H Reset value Table 15. CL: PCA Counter Low CL Address 0E9H Reset value To use one of the ...
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Software Timer/ Compare Mode Figure 10. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable Only for Module 4 4188A–8051–10/02 The PCA modules can be used as software timers by ...
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High Speed Output Mode Figure 11. PCA High Speed Output Mode Write to Reset CCAPnL Write to CCAPnH 0 Enable 1 TS8xC51Rx2 30 In this mode the CEX output (on port 1) associated with the PCA module will toggle each ...
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Pulse Width Modulator Mode PCA Watchdog Timer 4188A–8051–10/02 All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM func- tion. The frequency of the output depends on the source for the PCA timer. All ...
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TS8xC51Rx2 32 changing the time base for other modules would not be a good idea. Thus, in most appli- cations the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. 4188A–8051–10/02 ...
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TS80C51Rx2 Serial I/O Port Framing Error Detection Figure 13. Framing Error Block Diagram SM0/FE SMOD1 Figure 14. UART Timings in Mode 1 RXD RI SMOD0=X FE SMOD0=1 4188A–8051–10/02 The serial I/O port in the TS80C51Rx2 is compatible with the serial ...
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Figure 15. UART Timings in Modes 2 and 3 SMOD0=0 SMOD0=1 SMOD0=1 Automatic Address Recognition Given Address TS8xC51Rx2 34 RXD Start Data byte bit The automatic address recognition feature is enabled when the ...
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Broadcast Address 4188A–8051–10/02 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit com- municate ...
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Reset Addresses TS8xC51Rx2 36 On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, ...
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Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected. SMOD0 must be set to ...
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TS8xC51Rx2 38 Table 19. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode 1, 2 ...
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Interrupt System Figure 16. Interrupt Control System INT0 TF0 INT1 TF1 PCA TF2 EXF2 Individual Enable 4188A–8051–10/02 The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, ...
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TS8xC51Rx2 40 Table 20. Priority Level Bit Values IPH.x IP low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be ...
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Table 22. IP Register IP - Interrupt Priority Register (B8h PPC PT2 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt ...
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TS8xC51Rx2 42 Table 23. IPH Register IPH - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Idle Mode Power-down Mode Figure 17. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase 4188A–8051–10/02 An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal ...
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TS8xC51Rx2 44 Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: If ...
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Hardware Watchdog Timer Using the WDT 4188A–8051–10/02 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) ...
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WDT during Power-down and Idle TS8xC51Rx2 46 Bit Bit Number Mnemonic Description Reset ...
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TM ONCE Mode (ON Chip Emulation) 4188A–8051–10/02 The ONCE mode facilitates testing and debugging of systems using TS8xC51Rx2 with- out removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following ...
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Power-Off Flag TS8xC51Rx2 48 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and ...
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Reduced EMI Mode 4188A–8051–10/02 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce ...
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TS83C51RB2/RC2/RD2 ROM ROM Structure ROM Lock System Encryption Array Program Lock Bits Signature bytes Verify Algorithm TS8xC51Rx2 50 The TS83C51RB2/RC2/RD2 ROM memory is divided in three different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. • the ...
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TS87C51RB2/RC2/RD2 EPROM EPROM Structure EPROM Lock System Encryption Array Program Lock Bits Signature bytes 4188A–8051–10/02 The TS87C51RB2/RC2/RD2 EPROM is divided in two different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. In addition a third non programmable ...
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EPROM Programming Set-up Modes Definition of Terms TS8xC51Rx2 52 In order to program and verify the EPROM or to read the signature bytes, the TS87C51RB2/RC2/RD2 is placed in specific set-up modes (See Figure 18.). Control and program signals must be ...
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PROGRAM SIGNALS* CONTROL SIGNALS MHz * See Table 31. for proper value on these inputs Programming Algorithm Verify algorithm 4188A–8051–10/02 Figure 18. Set-Up Modes Configuration EA/VPP ALE/PROG P0.0-P0.7 RST PSEN P1.0-P1.7 P2.6 P2.7 P2.0-P2.5 P3.3 P3.4-P3.5 P3.6 ...
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Figure 19. Programming and Verification Signal’s Waveform A0-A12 D0-D7 ALE/PROG 12.75V 5V EA/VPP 0V Control signals EPROM Erasure (Windowed Packages Only) Erasure Characteristics Signature Bytes TS8xC51Rx2 54 Programming Cycle Data In 100µs Erasing the EPROM erases the code array, the ...
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TS8xC51Rx2 55 ...
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Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias commercial......................................................0°C to 70° industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage ........................................-0 ...
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Table 34. DC Parameters in Standard Voltage Symbol Parameter Output High Voltage, ports Output High Voltage, port 0 OH1 V Output High Voltage,ALE, PSEN OH2 R RST Pulldown Resistor RST Logical ...
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DC Parameters for Low Voltage TS8xC51Rx2 0°C to +70° -40°C to +85° Table 35. DC Parameters for Low Voltage Symbol ...
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Notes under reset is measured with all output pins disconnected; XTAL1 driven with 0 0.5V; XTAL2 N.C RST = Port ...
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Reset = Vss after a high pulse during at least 24 clock cycles Reset = Vss after a high pulse during at least 24 clock cycles TS8xC51Rx2 60 Figure 21. Operating I Test Condition ...
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AC Parameters Explanation of the AC Symbols 4188A–8051–10/02 Figure 24. Clock Signal Waveform for I V -0.5V 0.7V CC 0.2V 0.45V T T CLCH CHCL 5ns. CLCH CHCL Each timing symbol has 5 characters. The first ...
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External Program Memory Characteristics TS8xC51Rx2 62 Example mode for a -V part at 20 MHz (T = 1/20 LLIV x= 22 (Table 40.) T= 50ns ...
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Table 39. AC Parameters for Fix Clock -V X2 mode 30 MHz -M 60 MHz Speed 40 MHz equiv. Symbol Min Max Min LHLL AVLL LLAX T ...
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External Program Memory Read Cycle Figure 25. External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics TS8xC51Rx2 CLCL T T LHLL LLIV T LLPL T PLPH ...
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Table 41. AC Parameters for a Fix Clock -V X2 mode 30 MHz Speed -M 60 MHz 40 MHz equiv. Symbol Min Max Min T 130 85 RLRH T 130 85 WLWH T 100 RLDV RHDX ...
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External Data Memory Write Cycle Figure 26. External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle TS8xC51Rx2 66 Table 42. AC Parameters for a Variable Clock: derating formula Standard ...
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ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode 4188A–8051–10/02 Figure 27. External Data Memory Read Cycle T LLDV T LLWL T AVDV T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR ...
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Shift Register Timing Waveforms Figure 28. Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI TS8xC51Rx2 68 Table 44. AC Parameters for a Variable Clock: derating formula Standard Symbol Type ...
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EPROM Programming and Verification Characteristics EPROM Programming and Verification Waveforms Figure 29. EPROM Programming and Verification Waveforms P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* P0 ALE/PROG EA CONTROL SIGNALS (ENABLE) * 8KB P2.4, 16KB P2.5, 32KB: up ...
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External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms Figure 30. External Clock Drive Waveforms Testing Input/Output Waveforms Figure 31. AC Testing Input/Output Waveforms INPUT/OUTPUT Float Waveforms Figure 32. Float Waveforms TS8xC51Rx2 70 ...
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Clock Waveforms Figure 33. Clock Waveforms STATE4 INTERNAL CLOCK P1P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN DATA P0 SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV DEST P0 MOV DEST ...
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... TS80C51RA2-MCE Romless TS80C51RA2-MIA Romless TS80C51RA2-MIB Romless TS80C51RA2-MIE Romless TS80C51RA2-LCA Romless TS80C51RA2-LCB Romless TS80C51RA2-LCE Romless TS80C51RA2-LIA Romless TS80C51RA2-LIB Romless TS80C51RA2-LIE Romless TS80C51RA2-VCA Romless TS80C51RA2-VCB Romless TS80C51RA2-VCE Romless TS80C51RA2-VIA Romless TS80C51RA2-VIB Romless TS80C51RA2-VIE Romless TS80C51RD2-MCA Romless TS80C51RD2-MCB Romless TS80C51RD2-MCE Romless TS80C51RD2-MCL Romless TS80C51RD2-MCM ...
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Part-number Memory size TS80C51RD2-LCM Romless TS80C51RD2-LIA Romless TS80C51RD2-LIB Romless TS80C51RD2-LIE Romless TS80C51RD2-LIL Romless TS80C51RD2-LIM Romless TS80C51RD2-VCA Romless TS80C51RD2-VCB Romless TS80C51RD2-VCE Romless TS80C51RD2-VCL Romless TS80C51RD2-VCM Romless TS80C51RD2-VIA Romless TS80C51RD2-VIB Romless TS80C51RD2-VIE Romless TS80C51RD2-VIL Romless TS80C51RD2-VIM Romless TS87C51RB2-MCA OTP 16k Bytes TS87C51RB2-MCB ...
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Part-number Memory size TS87C51RC2-MCA OTP 32k Bytes TS87C51RC2-MCB OTP 32k Bytes TS87C51RC2-MCE OTP 32k Bytes TS87C51RC2-MIA OTP 32k Bytes TS87C51RC2-MIB OTP 32k Bytes TS87C51RC2-MIE OTP 32k Bytes TS87C51RC2-LCA OTP 32k Bytes TS87C51RC2-LCB OTP 32k Bytes TS87C51RC2-LCE OTP 32k Bytes TS87C51RC2-LIA ...
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Part-number Memory size TS87C51RD2S287-MCA OTP 64k Bytes TS87C51RD2S287-KCB OTP 64k Bytes TS87C51RD2S287-KCE OTP 64k Bytes TS87C51RD2S287-KCL OTP 64k Bytes TS87C51RD2S287-KCM OTP 64k Bytes TS87C51RD2-LIA OTP 64k Bytes TS87C51RD2-LIB OTP 64k Bytes TS87C51RD2-LIE OTP 64k Bytes TS87C51RD2-LIL OTP 64k Bytes TS87C51RD2-LIM ...
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Part-number Memory size TS83C51RB2-VCE ROM 16k Bytes TS83C51RB2-VIA ROM 16k Bytes TS83C51RB2-VIB ROM 16k Bytes TS83C51RB2-VIE ROM 16k Bytes TS83C51RC2-MCA ROM 32k Bytes TS83C51RC2-MCB ROM 32k Bytes TS83C51RC2-MCE ROM 32k Bytes TS83C51RC2-MIA ROM 32k Bytes TS83C51RC2-MIB ROM 32k Bytes TS83C51RC2-MIE ...
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Part-number Memory size TS83C51RD2-LCB ROM 64k Bytes TS83C51RD2-LCE ROM 64k Bytes TS83C51RD2-LCL ROM 64k Bytes TS83C51RD2-LCM ROM 64k Bytes TS83C51RD2-LIA ROM 64k Bytes TS83C51RD2-LIB ROM 64k Bytes TS83C51RD2-LIE ROM 64k Bytes TS83C51RD2-LIL ROM 64k Bytes TS83C51RD2-LIM ROM 64k Bytes TS83C51RD2-VCA ...
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Package Drawings PLCC44 TS8xC51Rx2 78 4188A–8051–10/02 ...
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PDIL40 4188A–8051–10/02 TS8xC51Rx2 79 ...
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VQFP44 TS8xC51Rx2 80 4188A–8051–10/02 ...
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VQFP64 4188A–8051–10/02 TS8xC51Rx2 81 ...
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PLCC68 TS8xC51Rx2 82 4188A–8051–10/02 ...
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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...