TS80C51RA2 Atmel Corporation, TS80C51RA2 Datasheet - Page 8

• Manufacturer Part Number: TS80C51RA2
• Description: High Performance 8-bit Microcontroller
• Manufacturer: Atmel Corporation

Pin Description for 64/68
pin Packages
8
Reset
ALE/PROG
PSEN
EA/V
XTAL1
XTAL2
Mnemonic
PP
TS8xC51Rx2
DIL
14
15
16
17
30
29
31
19
18
9
Pin Number
LCC
16
17
18
19
10
33
32
35
21
20
VQFP 1.4
Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1s
written to them are pulled high by the internal pull ups and can be used as inputs.
As inputs, pins that are externally pulled low will source current because of the internal
pull-ups.
Refer to the previous pin description for other pins.
10
12
13
27
26
29
15
14
11
4
Type
O (I)
O
O
O
O
I
I
I
I
I
Name And Function
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V
external capacitor to V
becomes an output during the time the internal reset is activated.
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during EPROM
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
External Access Enable/Programming Supply Voltage: EA must be externally held
low to enable the device to fetch code from external program memory locations 0000H
and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device
executes from internal program memory unless the program counter contains an
address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless
devices. This pin also receives the 12.75V programming supply voltage (V
EPROM programming. If security level 1 is programmed, EA will be internally latched
on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2: Output from the inverting oscillator amplifier
CC.
If the hardware watchdog reaches its time-out, the reset pin
SS
permits a power-on reset using only an
4188A–8051–10/02
PP
) during