74LVC74AD,118 NXP Semiconductors, 74LVC74AD,118 Datasheet - Page 8

• Manufacturer Part Number: 74LVC74AD,118
• Description: IC DUAL D-TYPE FLIP-FLOP 14-SOIC
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC74AD,118

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 250MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: 74LVC
• Logic Type: D-Type Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 7 ns
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: SO
• Low Level Output Current: 24mA
• Frequency (max): 120MHz
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2305-2; 74LVC74AD-T; 935260734118

NXP Semiconductors
74LVC74A_6
Product data sheet
Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths,
V
V
V
and the nRD to nCP recovery time
M
M
OL
= 1.5 V at V
= 0.5
and V
OH
V
CC
are typical output voltage levels that occur with the output load.
CC
at V
2.7 V;
CC
< 2.7 V;
nCP input
nSD input
nRD input
nQ output
nQ output
GND
GND
GND
V
V
V
V
OH
OH
OL
OL
V
V
V
I
I
I
V
M
Rev. 06 — 4 June 2007
Dual D-type flip-flop with set and reset; positive-edge trigger
t
V
V
W
M
M
t
t
PLH
PHL
V
M
t
W
t
t
PHL
PLH
V
M
mna423
t
rec
74LVC74A
© NXP B.V. 2007. All rights reserved.
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