TS8388BCFX/X Atmel Corporation, TS8388BCFX/X Datasheet
TS8388BCFX/X
Related parts for TS8388BCFX/X
TS8388BCFX/X Summary of contents
Page 1
MAIN FEATURES § 8-bit resolution. § ADC gain adjust. § 1.5 GHz full power input bandwidth. § 1 Gsps (min) sampling rate. § SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc @ Gsps, F ...
Page 2
Preliminary Beta-Site Specification 1. SIMPLIFIED BLOCK DIAGRAM.................................................................................................................................... 3 2. FUNCTIONAL DESCRIPTION........................................................................................................................................ 3 3. SPECIFICATIONS............................................................................................................................................................. 4 3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) ...............................................................................................................................4 3.2. RECOMMENDED CONDITIONS OF USE..........................................................................................................................................................4 3.3. ELECTRICAL OPERATING CHARACTERISTICS .............................................................................................................................................5 3.4. TIMING DIAGRAMS.............................................................................................................................................................................................9 3.5. EXPLANATION OF TEST ...
Page 3
SIMPLIFIED BLOCK DIAGRAM MASTER/SLAVE TRACK & HOLD AMPLIFIER VIN,VINB G=2 T/H G=1 CLOCK CLK, CLKB BUFFER DRRB DR,DRB 2. FUNCTIONAL DESCRIPTION The TS8388BF bit 1GSPS ADC based on an advanced high speed bipolar technology (B6HF from ...
Page 4
Preliminary Beta-Site Specification 3. SPECIFICATIONS 3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between V ...
Page 5
ELECTRICAL OPERATING CHARACTERISTICS VEE = DVEE = - Digital outputs differentially terminated ; Tj (typical Full temperature range : -55(-0/+5) C < Tc ...
Page 6
Preliminary Beta-Site Specification Parameter DIGITAL OUTPUTS (notes 1,6) Single ended or differential input mode clock duty cycle (CLK,CLKB), Binary output data format, Tj (typical Full temperature range :-55(-0/+5) C < < +125(-5/+0) ...
Page 7
Parameter TRANSIENT PERFORMANCE Bit Error Rate Gsps Fin = 62.5 MHz ADC settling time 400 mVpp In inB Overvoltage recovery time AC PERFORMANCE Single ended or differential input and clock mode clock ...
Page 8
Preliminary Beta-Site Specification Parameter SWITCHING PERFORMANCE AND CHARACTERISTICS – See Timing Diagrams Figure 1, Figure 2 Maximum clock frequency Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output ...
Page 9
TIMING DIAGRAMS ( IN, INB X N-1 (CLK, CLKB) 1360 p s DIGITAL 1000 Data Ready (DR, DRB) D ...
Page 10
Preliminary Beta-Site Specification 3.5. EXPLANATION OF TEST LEVELS D 100 % wafer tested at + 100% production tested at + 100 % production tested at +25 C III Sample tested only at specified temperatures IV Parameter ...
Page 11
FUNCTIONS DESCRIPTION Name Function VCC Positive power supply VEE Analog negative power supply VPLUSD Digital positive power supply GND Ground VIN, VINB Differential analog inputs CLK, CLKB Differential clock inputs <D0:D7> Differential output data port <D0B:D7B> DRB ...
Page 12
Preliminary Beta-Site Specification 4. PACKAGE DESCRIPTION. 4.1. TS8388BF PIN DESCRIPTION Symbol Pin number GND 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58 16, 17, 18, 68 PLUSD V 26, ...
Page 13
TS8388BF PINOUT TOP VIEW : VPLUSD D2 D2B D1 D1B D0 D0B TS8388BF VPLUSD D6B D6 D7B D7 ORB OR Preliminary Beta-Site Specification 13 ...
Page 14
Preliminary Beta-Site Specification 4.3. OUTLINE DIMENSIONS – 68 PINS CQFP Pin N TS8388BF pins Ceramic Quad Flat Pack – Top view 0.8 BCS 20.32 BSC 0.050 BCS o 1 index 1.27 BSC . CQFP 68 .950 ± ...
Page 15
THERMAL CHARACTERISTICS Although the power dissipation is low for this performance, the use of a heat sink is mandatory. You will find here below some advise on this topics. 4.4.1. T HERMAL RESISTANCE FROM JUNCTION TO AMBIENT The following ...
Page 16
Preliminary Beta-Site Specification 5. TYPICAL CHARACTERIZATION RESULTS 5.1. STATIC LINEARITY – MSPS / FIN = 10 MHZ 5.1. NTEGRAL ON INEARITY 5.1. IFFERENTIAL ON INEARITY ...
Page 17
EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION Effective ...
Page 18
Preliminary Beta-Site Specification 5.3. TYPICAL FFT RESULTS 5.3 = SPS 5.3. GSPS 495 ...
Page 19
SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE 5.4.1. SAMPLING FREQUENCY F S Full Scale ENOB = 6 ...
Page 20
Preliminary Beta-Site Specification 5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY Fs=1 Gsps, Fin = 1600 MHz, Full Scale input (FS Clock duty cycle 50 / 50, Binary/Gray output coding, fully differential or single-ended analog ...
Page 21
EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fin = Clock duty cycle Binary output coding 8 Fin= FS/2 ...
Page 22
Preliminary Beta-Site Specification 5.8. TS8388BF ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE -40 - GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBFs -60 ...
Page 23
TYPICAL FULL POWER INPUT BANDWIDTH 1.5 GHz (-2dBm full power input) 100 300 Power consumption versus junction temperature ...
Page 24
Preliminary Beta-Site Specification 5.10. ADC STEP RESPONSE Test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps. Note : This step response was obtained with the TSEV8388B chip on board (device in die form). ...
Page 25
DEFINITION OF TERMS Bit Error Rate (BER) Full power input (BW) bandwidth (SINAD) Signal to noise and distortion ratio (SNR) Signal to noise ratio (THD) Total harmonic distorsion Spurious free dynamic (SFDR) range (ENOB) Effective Number Of Bits (DNL) ...
Page 26
Preliminary Beta-Site Specification Data Ready reset delay (TRDR) Rise time (TR) Fall time (TF) Power supply (PSRR) rejection ratio (NRZ) Non return to zero InterModulation Distortion The two tones intermodulation distortion ( IMD ) rejection is the ratio of either ...
Page 27
APPLYING THE TS8388BF 7.1. TIMING INFORMATIONS 7.1.1. T TS8388BF IMING VALUE FOR Timing values as defined in 3.3 are advanced data, issuing from electric simulations and first characterizations results fitted with measurements. Timing values are given at CQFP68 package ...
Page 28
Preliminary Beta-Site Specification 7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND 7.2.1. DATA READY OUTPUT SIGNAL RESET The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB ...
Page 29
This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the ...
Page 30
Preliminary Beta-Site Specification Single ended Clock input (Ground common mode) VCLK common mode = 0 Volt VCLKB=0 Volt 4 dBm typical clock input power level (into 50 ohms termination resistor) [V] VCLK +0.5V -0.5V Note not exceed ...
Page 31
CLOCK SIGNAL DUTY CYCLE ADJUST At fast sampling rates Gsps and above), the device performance ( especially the SNR ) may be improved by tuning the Clock duty cycle (CLK,CLKB). In single ended configuration, when using a ...
Page 32
Preliminary Beta-Site Specification 7.7. DIGITAL OUTPUTS The TS8388BF differential output buffers are internally 75 ohms loaded. The 75 ohms resistors are connected to the digital ground pins through a - 0.8v level shift diode (see Figures 3,4,5 on next page). ...
Page 33
DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS ( VPLUSD = 0V -0. DVEE VPLUSD = 0V -0. DVEE VPLUSD = 0V -0. DVEE ECL LEVELS FOR ...
Page 34
Preliminary Beta-Site Specification 7.7.2. DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS ( VPLUSD = 2.4V 1. DVEE VPLUSD = 2.4V 1. DVEE VPLUSD = 2.4V 1. DVEE TS8388BF 34 34 LVDS ...
Page 35
OUT OF RANGE BIT An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale. When the analog input exceeds the ...
Page 36
Preliminary Beta-Site Specification 7.11. ADC GAIN CONTROL PIN 60 The ADC gain is adjustable by the means of the pin 60 (input impedance parallel with 2pF) The gain adjust transfert function is given below : 1,20 1,15 ...
Page 37
EQUIVALENT INPUT / OUTPUT SCHEMATICS 8.1. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS VCC=+5V -0. -5.8V 50 E21V VIN Pad capacitance 340fF 5.8V 0.8V Note : the ESD protection equivalent ...
Page 38
Preliminary Beta-Site Specification 8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS VEE OUT Pad capacitance 180 fF VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. 8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS V ...
Page 39
GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS Pad capacitance 180fF GORB: gray or binary select input; floating or tied to VCC -> binary V C ...
Page 40
Preliminary Beta-Site Specification 8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS Actual protection range: 6.6V above VEE, In fact stress above GND are clipped by the CB diode used for Tj monitoring Pad capacitance 180 fF ...
Page 41
TSEV8388BF : DEVICE EVALUATION BOARD For complete specification, see separate TSEV8388BF document. GENERAL DESCRIPTION The TSEV8388BF Evaluation Board (CEB board which has been designed in order to facilitate the evaluation and the characterization of the TS8388BF device ...
Page 42
Preliminary Beta-Site Specification 10. ORDERING INFORMATION 10.1. PACKAGE DEVICE Manufacturer prefix Device or family Temperature range : M : -55 < < 125 -40 < Tc < + < Tc ...
Page 43
Objective specification This datasheet contains target and goal specification for discussion with customer and application validation. Target specification This datasheet contains target and goal specification for product development. Preliminary specification This datasheet contains preliminary data. Additional data may be Alpha-site ...
Page 44
Preliminary Beta-Site Specification Atmel Grenoble, formerly Thomson-CSF Semiconducteurs Specifiques, an Atmel Group Company. Information furnished is believed to be accurate and reliable. However Atmel Grenoble assumes no responsability for the consequences of use of such information nor for any infringement ...