LTC1197 Linear Technology, LTC1197 Datasheet - Page 16

• Manufacturer Part Number: LTC1197
• Description: 10-Bit/ 500ksps ADCs in MSOP with Auto Shutdown
• Manufacturer: Linear Technology

LTC1197/LTC1197L
LTC1199/LTC1199L
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the ADC operating on 3V or
9V supplies. The requirement to achieve this is that the
outputs of CS, CLK and D
to trip the equivalent inputs of the ADC and the output of
the ADC must be able to toggle the equivalent input of the
MPU (see typical curve of Digital Input Logic Threshold vs
Supply Voltage). With the LTC1197 operating on a 9V
supply, the output of D
9V output may damage the MPU running off a 5V supply.
The way to solve this problem is to have a resistor divider
on D
MPU input. It should be noted that to get full shutdown, the
CS input of the ADC must be driven to the V
would require adding a level shift circuit to the CS signal
in Figure 4.
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1197/LTC1197L/LTC1199/LTC1199L should be
used with an analog ground plane and single point ground-
ing techniques. The GND pin should be tied directly to the
ground plane. The V
ground plane using a 1 F tantalum capacitor with leads as
short as possible. All analog inputs should be referenced
directly to the single point ground. Digital inputs and
outputs should be shielded from and/or routed away from
the reference and analog circuitry.
16
A
COMMON MODE RANGE
DIFFERENTIAL INPUTS
PPLICATI
Figure 4. Interfacing a 9V-Powered LTC1197 to a 5V System
OUT
(Figure 4) and connect the center point to the
LEVEL SHIFT
0V TO 6V
OPTIONAL
O
CS
+IN
–IN
GND
U
9V
LTC1197
CC
OUT
S
pin should be bypassed to the
IN
D
may go between 0V and 9V. The
V
I FOR ATIO
CLK
V
OUT
REF
U
from the MPU have to be able
CC
9V
4.7k
6V
4.7 F
W
4.7k
CC
P1.4
P1.3
P1.2
voltage. This
(e.g. 8051)
MPU
U
1197/99 F04
5V
SAMPLE-AND-HOLD
The LTC1197/LTC1197L/LTC1199/LTC1199L provide a
built-in sample-and-hold (S /H) function to acquire sig-
nals. The S /H of the LTC1197/LTC1197L acquires input
signals for the “+” input relative to the “–” input during the
t
LTC1199L can sample input signals from the “+” input
relative to ground and from the “–” input relative to ground
in addition to acquiring signals from the “+” input relative
to the “–” input (see Figure 5) during t
Single-Ended Inputs
The sample-and-hold of the LTC1199/LTC1199L allows
conversion of rapidly varying signals. The input voltage is
sampled during the t
sampling interval begins as the ODD/SGN bit is shifted in
and continues until the falling CLK edge after the dummy
bit is received. On this falling edge, the S/H goes into hold
mode and the conversion begins.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
age on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 10.5 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
Where f(“–”) is the frequency of the “–” input voltage,
V
CLK. In most cases V
60Hz signal on the “–” input to generate a 1/4LSB error
(1.22mV) with the converter running at CLK = 7.2MHz, its
peak value would have to be 2.22V.
SMPL
PEAK
V
ERROR (MAX)
time (see Figure 1). However the S /H of the LTC1199/
is its peak amplitude and f
= V
PEAK
SMPL
ERROR
• 2 • • f(“–”) • 10.5/f
time as shown in Figure 5. The
will not be significant. For a
CLK
is the frequency of the
SMPL
.
CLK