LTC1257C Linear Technology, LTC1257C Datasheet - Page 5

• Manufacturer Part Number: LTC1257C
• Description: Complete Single Supply 12-Bit Voltage Output DAC in SO-8
• Manufacturer: Linear Technology

PI FU CTIO S
CLK (Pin 1): The TTL level input for the serial interface
clock.
D
Data on the D
rising edge of the serial clock.
LOAD (Pin 3): The TTL level input for the serial interface
load control. Data is loaded from the shift register into the
DAC register, thus updating the DAC output when LOAD is
pulled low. The DAC register is transparent as long as
LOAD is held low.
D
becomes valid on the rising edge of the serial clock. The
D
inverter. Multiple LTC1257s may be cascaded by connect-
ing the D
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
IN
OUT
OUT
0.5
0.0
U
(Pin 2): The TTL level input for the serial interface data.
0
(Pin 4):
Differential Nonlinearity (DNL)
pin is driven from GND to V
512
OUT
U
1024
IN
pin to the D
1536
pin is latched into the shift register on the
The output of the shift register which
CODE
2048 2560
U
IN
3072 3584 4098
pin of the next chip.
W
1257 TA05
CC
U
by an internal CMOS
70
60
50
40
30
20
10
0
0.01
Reference Compensation
Resistance vs C
0.1
C
L
L
( F)
GND (Pin 5): Ground.
REF (Pin 6): The output of the 2.048V reference and the
input to the DAC resistor ladder. An external reference with
voltage from 2.475V to V
the internal reference.
V
sourcing 2mA over temperature while pulling within 2.7V
of V
200 equivalent resistance.
V
15.75V. Requires a bypass capacitor to ground.
1
OUT
CC
CC
(Pin 8): The positive supply input. 4.75V
(Pin 7): The buffered DAC output is capable of
. The output will pull to ground through an internal
10
1257 G11
100
CC
Broadband Noise
– 2.7V may be used to override
CODE = FFFH
BW = 3Hz TO 1MHz
GAIN = 1100
TIME = 5ms/DIV
LTC1257
V
CC
1257 G12
5