LTC1257C Linear Technology, LTC1257C Datasheet - Page 8

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LTC1257C

Manufacturer Part Number
LTC1257C
Description
Complete Single Supply 12-Bit Voltage Output DAC in SO-8
Manufacturer
Linear Technology
Datasheet

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OPERATIO
Serial Interface
The data on the D
on the rising edge of the clock. The MSB is loaded first and
the LSB last. The DAC register loads the data from the shift
register when LOAD is pulled low, and remains transpar-
ent until LOAD is pulled high and the data is latched.
An internal 5V regulator provides the supply for the digital
logic. By limiting the internal digital signal swings to 5V,
digital noise is reduced. The buffered output of the 12-bit
shift register is available on the D
from GND to V
Multiple LTC1257s may be daisy chained together by
connecting the D
while the clock and load signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the LOAD signal is pulled low to update all
of them simultaneously. The maximum clocking rate is
1.4MHz.
LTC1257
8
TYPICAL
CONTROL OUTPUT
15V
A
CC
DAC with External Reference
PPLICATI
.
OUT
0.1 F
IN
U
input is loaded into the shift register
V
OUT
pin to the D
GND
V
CC
LTC1257
LT1021-10
V
OUT
IN
REF
O
GND
LOAD
D
OUT
CLK
OUT
D
IN
U
IN
pin of the next chip,
pin which will swing
S
1257 TA03
P
Reference
The LTC1257 includes an internal 2.048V reference, mak-
ing 1LSB equal to 500 V. The internal reference output is
turned off when the pin is forced above the reference
voltage, allowing an external reference to be connected to
the reference pin. The external reference must be greater
than 2.475V and less than V
driving the 10k minimum DAC resistor ladder.
If the reference output is driving a large capacitive load, a
series resistor must be added to insure stability. For any
capacitive load greater than 1 F, a 10 series resistor will
suffice.
Voltage Output
The LTC1257 voltage output is able to pull within 2.7V of
V
a 200 equivalent impedance pulls the output to ground.
The output is protected against short circuits and is able
to drive up to a 500pF capacitive load without oscillation.
If digital noise on the output causes a problem, a simple
100 , 0.1 F RC circuit can be used to filter the noise.
CC
while sourcing 2mA. A internal NMOS transistor with
D
CLK
LOAD
D
IN
OUT
Filtering V
GND
V
V
LTC1257
CC
CC
V
REF
10
5%
REF
V
CC
0.1 F
1 F
OUT
and V
– 2.7V, and be capable of
100
OUT
5%
0.1 F
1257 TA06
V
OUT

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