LTC2205 Linear Technology, LTC2205 Datasheet - Page 28

• Manufacturer Part Number: LTC2205
• Description: (LTC2204 / LTC2205) 65Msps/40Msps
• Manufacturer: Linear Technology

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LTC2205/LTC2204
APPLICATIONS INFORMATION
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven.
OV
of the ADC. OGND can be powered with any voltage from
ground up to 1V and must be less than OV
outputs will swing between OGND and OV
Internal Dither
The LTC2205/LTC2204 are 16-bit ADCs with very linear
transfer functions; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
28
DD
can be powered with any logic voltage up to the V
PC BOARD
Figure 13. Descrambling a Scrambled Digital Output
LTC2205/
LTC2204
DD
, should be tied
DD
DD
.
. The logic
CLKOUT
D15/D0
D14/D0
D2/D0
D1/D0
OF
D0
DD
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The
dither DAC is calibrated to result in less than 0.5dB eleva-
tion in the noise fl oor of the ADC, as compared to the
noise fl oor with dither off.
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the input
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
As shown in Figure 14, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
FPGA
•
•
•
D15
D14
D2
D1
D0
22054 F13
22054fb