LTC3738 Linear Technology, LTC3738 Datasheet - Page 23

• Manufacturer Part Number: LTC3738
• Description: 3-Phase Buck Controller
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
Undervoltage Reset
In the event that the input power source to the IC (V
drops below 4V, the SS capacitor will be discharged to
ground and the controller will be shut down. When V
rises above 4V, the SS capacitor will be allowed to re-
charge and initiate another soft-start turn-on attempt. This
may be useful in applications that switch between two
supplies that are not diode connected, but note that this
cannot make up for the resultant interruption of the
regulated output.
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency f
the PLLFLTR pin of 1.2V corresponds to a frequency of
approximately 350kHz. The nominal operating frequency
range of the IC is 210kHz to 530kHz.
The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the
external and internal oscillators. This type of phase
detector will not lock the internal oscillator to harmonics
of the input frequency. The PLL hold-in range, ∆f
equal to the capture range, ∆f
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 8.
If the external frequency (f
lator frequency, f
pulling up the PLLFLTR pin. When the external frequency
is less than f
down the PLLFLTR pin. If the external and internal fre-
quencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
∆f
H
= ∆f
C
= ±0.5 f
OSC
, current is sunk continuously, pulling
OSC
U
O
, current is sourced continuously,
U
PLLIN
C
) is greater than the oscil-
:
W
O
. A voltage applied to
U
H
, is
CC
CC
)
stable operating point, the phase comparator output is
open and the filter capacitor C
FCB/SYNC pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple ICs for a phase-locked system, the PLLFLTR
pin of the master oscillator should be biased at a voltage
that will guarantee the slave oscillator(s) ability to lock
onto the master’s frequency. A voltage of 1.7V or below
applied to the master oscillator’s PLLFLTR pin is recom-
mended in order to meet this requirement. The resultant
operating frequency will be approximately 500kHz for
1.7V.
The loop filter components (C
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
acquires lock. Typically R
0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, t
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
t
FCB/SYNC
ON MIN
(
EXTERNAL
Figure 8. Phase-Locked Loop Block Diagram
)
OSC
<
V f
LP
V
IN
OUT
( )
OSCILLATOR
and R
DETECTOR/
PHASE
ON(MIN)
FREQUENCY
DETECTOR
DIGITAL
PHASE/
LP
LP
determine how fast the loop
, is the smallest time duration
=10k and C
LP
LP
holds the voltage. The IC
2.4V
, R
LP
3738 F08
) smooth out the
LTC3738
LP
R
PLLFLTR
10k
ranges from
LP
OSC
23
C
LP
3738f