LTC4269-1 Linear Technology Corporation, LTC4269-1 Datasheet - Page 11

• Manufacturer Part Number: LTC4269-1
• Description: IEEE 802.3 At PD And Synchronous No-Opto Flyback Controller
• Manufacturer: Linear Technology Corporation

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PIN FUNCTIONS
Information section for details. This pin is used for the
UVLO function of the switching regulator. The PD interface
section has an internal UVLO.
SENSE
These pins are used to measure primary-side switch cur-
rent through an external sense resistor. Peak primary-side
current is used in the converter control loop. Make Kelvin
connections to the sense resistor R
problems. SENSE
current (V
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
C
Connect a capacitor from C
the effects of parasitic resistances in the feedback sensing
path. A 0.1μF ceramic capacitor suffi ces for most applica-
tions. Short this pin to GND when load compensation is
not needed.
R
Connect a resistor from R
pensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
CMP
CMP
(Pin 21): Load Compensation Capacitive Control.
(Pin 22): Load Compensation Resistive Control.
–
, SENSE
CMP
at its maximum voltage) SENSE pins have
+
–
(Pins 19, 20): Current Sense Inputs.
connects to the GND side. At maximum
CMP
CMP
to GND in order to reduce
to GND in order to com-
SENSE
to reduce noise
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (R
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic cur-
rents fl ow during voltage transitions. See the Applications
Information section for details.
V
to V
Pin 27 must be electrically tied together at the package.
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedence signals power-up completion. PWRGD
is referenced to V
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain. Low impedance signals power-up completion.
PWRGD is referenced to V
V
port power through the input diode bridge.
Exposed Pad (Pin 33): Ground. This is the negative rail
connection for both signal ground and gate driver grounds
of the fl yback controller. This pin should be connected to
V
NEG
PORTP
NEG
PORTN
.
(Pins 26, 27): System Negative Rail. Connects V
(Pin 32): Positive Power Input. Tie to the input
through an internal power MOSFET. Pin 26 and
NEG
and features a 14V clamp.
PORTN
.
PGDLY
LTC4269-1
) to set delay from
11
42691f
NEG